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參數資料
| 型號： | ADSP-21262SBBC-150 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數字信號處理 |
| 英文描述： | Embedded Processor |
| 中文描述： | 16-BIT, 50 MHz, OTHER DSP, PBGA136 |
| 封裝： | MO-205AE, BGA-136 |
| 文件頁數： | 11/48頁 |
| 文件大小： | 401K |
| 代理商： | ADSP-21262SBBC-150 |
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ADSP-21262
Rev. B
|
Page 11 of 48
|
August 2005
PIN FUNCTION DESCRIPTIONS
ADSP-21262 pin definitions are listed below. Inputs identified
as synchronous (S) must meet timing requirements with respect
to CLKIN (or with respect to TCK for TMS, TDI). Inputs iden-
tified as asynchronous (A) can be asserted asynchronously to
CLKIN (or to TCK for TRST). Tie or pull unused inputs to
V
DDEXT
or GND, except for the following:
DAI_Px, SPICLK, MISO, MOSI, EMU, TMS,TRST, TDI
and AD15–0 (NOTE: These pins have internal pull-up
resistors.)
The following symbols appear in the Type column of
Table 2
:
A = asynchronous, G = ground, I = input, O = output,
P = power supply, S = synchronous, (A/D) = active drive,
(O/D) = open drain, and T = three-state.
Table 2. Pin Descriptions
Pin
AD15–0
Type
I/O/T
State During and
After Reset
AD15–0 pins are
driven low both
during and after
reset
Function
Parallel Port Address/Data.
The ADSP-21262 parallel port and its corresponding
DMA unit output addresses and data for peripherals on these multiplexed pins. The
multiplex state is determined by the ALE pin. The parallel port can operate in either
8-bit or 16-bit mode. Each AD pin has a 22.5 k
internal pull-up resistor. See
Address
Data Modes on Page 14
for details of the AD pin operation.
For 8-bit mode: ALE is automatically asserted whenever a change occurs in the
upper 16 external address bits, A23–8; ALE is used in conjunction with an external
latch to retain the values of the A23–8.
For 16-bit mode: ALE is automatically asserted whenever a change occurs in the
address bits, A15–0; ALE is used in conjunction with an external latch to retain the
values of the A15–0. To use these pins as flags (FLAG15–0) set (=1) Bit 20 of the
SYSCTL register and disable the parallel port. See
Table 3 on Page 14
for a list of how
the AD15–0 pins map to the flag pins. When configured in the IDP_PDAP_CTL
register, the IDP Channel 0 can use these pins for parallel input data.
Parallel Port Read Enable.
RD is asserted low whenever the DSP reads 8-bit or
16-bit data from an external memory device. When AD15–0 are flags, this pin
remains deasserted.
Parallel Port Write Enable.
WR is asserted low whenever the DSP writes 8-bit or
16-bit data to an external memory device. When AD15–0 are flags, this pin remains
deasserted.
Parallel Port Address Latch Enable.
ALE is asserted whenever the DSP drives a
new address on the parallel port address pin. On reset, ALE is active high. However,
it can be reconfigured using software to be active low. When AD15–0 are flags, this
pin remains deasserted.
Flag Pins.
Each FLAG pin is configured via control bits as either an input or output.
As an input, it can be tested as a condition. As an output, it can be used to signal
external peripherals. These pins can be used as an SPI slave select output during SPI
mastering. These pins are also multiplexed with the IRQx and the TIMEXP signals.
In SPI master boot mode, FLAG0 is the slave select pin that must be connected to
an SPI EPROM. FLAG0 is configured as a slave select during SPI master boot. When
Bit 16 is set (=1) in the SYSCTL register, FLAG0 is configured as IRQ0.
When Bit 17 is set (=1) in the SYSCTL register, FLAG1 is configured as IRQ1.
When Bit 18 is set (=1) in the SYSCTL register, FLAG2 is configured as IRQ2.
When Bit 19 is set (=1) in the SYSCTL register, FLAG3 is configured as TIMEXP, which
indicates that the system timer has expired.
RD
O
Output only, driven
high
1
WR
O
Output only, driven
high
1
ALE
O
Output only, driven
low
1
FLAG3–0
I/O/A
Three-state
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| ADSP-21262SBBCZ150 | 功能描述:IC DSP 32BIT 150MHZ 136-CSPBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數字式信號處理器） 系列:SHARC® 標準包裝:40 系列:TMS320DM64x, DaVinci™ 類型:定點 接口:I²C，McASP，McBSP 時鐘速率:400MHz 非易失內存:外部 芯片上RAM:160kB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:0°C ~ 90°C 安裝類型:表面貼裝 封裝/外殼:548-BBGA，FCBGA 供應商設備封裝:548-FCBGA（27x27） 包裝:托盤 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
| ADSP-21262SKATZ-200 | 制造商:Analog Devices 功能描述: |
| ADSP-21262SKBC-200 | 功能描述:IC DSP 32BIT 200MHZ 136-CSPBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - DSP（數字式信號處理器） 系列:SHARC® 標準包裝:2 系列:StarCore 類型:SC140 內核 接口:DSI，以太網，RS-232 時鐘速率:400MHz 非易失內存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，FCBGA 供應商設備封裝:431-FCPBGA（20x20） 包裝:托盤 |
| ADSP-21262SKBC200R | 制造商:Analog Devices 功能描述:DSP Floating-Point 32-Bit 200MHz 200MIPS 136-Pin CSP-BGA T/R |
| ADSP-21262SKBC-200X | 制造商:Analog Devices 功能描述: |
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