
ADSP-21262
Rev. B
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Page 3 of 48
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August 2005
TABLE OF CONTENTS
General Description ................................................. 4
ADSP-21262 Family Core Architecture ...................... 4
ADSP-21262 Memory and I/O Interface Features ......... 6
Target Board JTAG Emulator Connector .................... 8
Development Tools ............................................... 9
Evaluation Kit ..................................................... 10
Designing an Emulator-Compatible
DSP Board (Target) ........................................... 10
Additional Information ......................................... 10
Pin Function Descriptions ........................................ 11
Address Data Pins as Flags ..................................... 14
Core Instruction Rate to CLKIN Ratio Modes ............. 14
Address Data Modes ............................................. 14
ADSP-21262 Specifications ....................................... 15
Recommended Operating Conditions ....................... 15
Electrical Characteristics ........................................ 15
Absolute Maximum Ratings ................................... 16
ESD Sensitivity .................................................... 16
Timing Specifications ........................................... 17
Output Drive Currents .......................................... 38
Test Conditions ................................................... 38
Capacitive Loading ............................................... 38
Environmental Conditions ..................................... 39
Thermal Characteristics ........................................ 39
136-Ball BGA Pin Configurations ............................... 41
144-Lead LQFP Pin Configurations ............................. 44
Package Dimensions ................................................ 45
Ordering Guide ...................................................... 46
REVISION HISTORY
8/05—Rev. A to Rev. B
Miscellaneous Format Updates.......................... Universal
Changed “Digital Audio Interface” to “Digital
Applications Interface”........................................ Global
Deleted ROM-Based Security from Page 8
Applied Corrections and Additional Information to:
Summary ............................................................ 1
Key Features ........................................................ 1
Additional Key Features .......................................... 2
General Description ............................................... 4
ADSP-21262 Family Core Architecture ...................... 4
Serial Ports .......................................................... 6
Parallel Port ......................................................... 8
Power Supplies ..................................................... 8
Evaluation Kit .................................................... 10
Pin Function Descriptions ..................................... 11
Recommended Operating Conditions ...................... 15
Clock Signals ...................................................... 19
Precision Clock Generator (Direct Pin Routing) ......... 23
Output Drive Currents ......................................... 38
Capacitive Loading .............................................. 38
Environmental Conditions .................................... 39
Thermal Characteristics ........................................ 39
Package Dimensions ............................................ 45
Ordering Guide .................................................. 46