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參數(shù)資料
| 型號： | ADSP-21262SBBCZ150 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | Embedded Processor |
| 中文描述： | 16-BIT, 50 MHz, OTHER DSP, PBGA136 |
| 封裝： | MO-205AE, BGA-136 |
| 文件頁數(shù)： | 12/48頁 |
| 文件大?。?/td> | 401K |
| 代理商： | ADSP-21262SBBCZ150 |
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Rev. B
|
Page 12 of 48
|
August 2005
ADSP-21262
DAI_P20–1
I/O/T
Three-state with
programmable
pull-up
Digital Applications Interface Pins
. These pins provide the physical interface to
the SRU. The SRU configuration registers define the combination of on-chip
peripheral inputs or outputs connected to the pin and to the pin’s output enable.
The configuration registers of these peripherals then determine the exact behavior
of the pin. Any input or output signal present in the SRU may be routed to any of
these pins. The SRU provides the connection from the serial ports, input data port,
precision clock generators, and timers to the DAI_P20–1 pins. These pins have
internal 22.5 k
pull-up resistors which are enabled on reset. These pull-ups can be
disabled in the DAI_PIN_PULLUP register.
Serial Peripheral Interface Clock Signal
. Driven by the master, this signal controls
the rate at which data is transferred. The master can transmit data at a variety of
baud rates. SPICLK cycles once for each bit transmitted. SPICLK is a gated clock that
is active during data transfers, only for the length of the transferred word. Slave
devices ignore the serial clock if the slave select input is driven inactive (HIGH).
SPICLK is used to shift out and shift in the data driven on the MISO and MOSI lines.
The data is always shifted out on one clock edge and sampled on the opposite edge
of the clock. Clock polarity and clock phase relative to data are programmable into
the SPICTL control register and define the transfer format. SPICLK has a 22.5 k
internal pull-up resistor. If SPI master boot mode is selected, MOSI and SPICLK pins
are driven during reset. These pins are not three-stated during reset in SPI master
boot mode.
Serial Peripheral Interface Slave Device Select
. An active low signal used to select
the DSP as an SPI slave device. This input signal behaves like a chip select, and is
provided by the master device for the slave devices. In multimaster mode the DSP’s
SPIDS signal can be driven by a slave device to signal to the DSP (as SPI master) that
an error has occurred, as some other device is also trying to be the master device.
If asserted low when the device is in master mode, it is considered a multimaster
error. For a single master, multiple-slave configuration where flag pins are used, this
pin must be tied or pulled high to V
DDEXT
on the master device. For ADSP-21262 to
ADSP-21262 SPI interaction, any of the master ADSP-21262’s flag pins can be used
to drive the SPIDS signal on the ADSP-21262 SPI slave device.
SPI Master Out Slave In
. If the ADSP-21262 is configured as a master, the MOSI pin
becomes a data transmit (output) pin, transmitting output data. If the ADSP-21262
is configured as a slave, the MOSI pin becomes a data receive (input) pin, receiving
input data. In an ADSP-21262 SPI interconnection, the data is shifted out from the
MOSI output pin of the master and shifted into the MOSI input(s) of the slave(s).
MOSI has a 22.5 k
internal pull-up resistor. If SPI master boot mode is selected,
MOSI and SPICLK pins are driven during reset. These pins are not three-stated during
reset in SPI master boot mode.
SPI Master In Slave Out
. If the ADSP-21262 is configured as a master, the MISO pin
becomes a data receive (input) pin, receiving input data. If the ADSP-21262 is
configured as a slave, the MISO pin becomes a data transmit (output) pin, trans-
mitting output data. In an ADSP-21262 SPI interconnection, the data is shifted out
from the MISO output pin of the slave and shifted into the MISO input pin of the
master. MISO has a 22.5 k
internal pull-up resistor. MISO can be configured as O/D
by setting the OPD bit in the SPICTL register.
Note:
Only one slave is allowed to transmit data at any given time.
To enable broadcast
transmission to multiple SPI slaves, the DSP’s MISO pin may be disabled by setting
(=1) Bit 5 (DMISO) of the SPICTL register.
Boot Configuration Select
. Selects the boot mode for the DSP. The BOOTCFG pins
must be valid before reset is asserted. See
Table 4 on Page 14
for a description of
the boot modes.
SPICLK
I/O
Three-state with
pull-up enabled
SPIDS
I
Input only
MOSI
I/O (O/D)
Three-state with
pull-up enabled
MISO
I/O (O/D)
Three-state with
pull-up enabled
BOOTCFG1–0
I
Input only
Table 2. Pin Descriptions (Continued)
Pin
Type
State During and
After Reset
Function
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