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參數資料
| 型號： | ADSP-21262SBBCZ150 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數字信號處理 |
| 英文描述： | Embedded Processor |
| 中文描述： | 16-BIT, 50 MHz, OTHER DSP, PBGA136 |
| 封裝： | MO-205AE, BGA-136 |
| 文件頁數： | 13/48頁 |
| 文件大小： | 401K |
| 代理商： | ADSP-21262SBBCZ150 |
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ADSP-21262
Rev. B
|
Page 13 of 48
|
August 2005
CLKIN
I
Input only
Local Clock In
. Used in conjunction with XTAL. CLKIN is the ADSP-21262 clock input.
It configures the ADSP-21262 to use either its internal clock generator or an external
clock source. Connecting the necessary components to CLKIN and XTAL enables the
internal clock generator. Connecting the external clock to CLKIN while leaving XTAL
unconnected configures the ADSP-21262 to use the external clock source such as
an external clock oscillator. The core is clocked either by the PLL output or this clock
input depending on the CLKCFG1–0 pin settings. CLKIN may not be halted,
changed, or operated below the specified frequency.
Crystal Oscillator Terminal
. Used in conjunction with CLKIN to drive an external
crystal.
Core/CLKIN Ratio Control
. These pins set the start up clock frequency. See
Table 5
for a description of the clock configuration modes.
Note that the operating frequency can be changed by programming the PLL multi-
plier and divider in the PMCTL register at any time after the core comes out of reset.
Reset Out/Local Clock Out
. Drives out the core reset signal to an external device.
CLKOUT can also be configured as a reset out pin (RSTOUT). The functionality can
be switched between the PLL output clock and reset out by setting Bit 12 of the
PMCTL register. The default is reset out.
Processor Reset
. Resets the ADSP-21262 to a known state. Upon deassertion, there
is a 4096 CLKIN cycle latency for the PLL to lock. After this time, the core begins
program execution from the hardware reset vector address. The RESET input must
be asserted (low) at power-up.
Test Clock (JTAG)
. Provides a clock for JTAG boundary scan. TCK must be asserted
(pulsed low) after power-up or held low for proper operation of the ADSP-21262.
Test Mode Select (JTAG)
. Used to control the test state machine. TMS has a
22.5 k
internal pull-up resistor.
Test Data Input (JTAG)
. Provides serial data for the boundary scan logic. TDI has a
22.5 k
internal pull-up resistor.
Test Data Output (JTAG)
. Serial scan output of the boundary scan path.
Test Reset (JTAG)
. Resets the test state machine. TRST must be asserted (pulsed
low) after power-up or held low for proper operation of the ADSP-21262. TRST has
a 22.5 k
internal pull-up resistor.
Emulation Status
. Must be connected to the ADSP-21262 Analog Devices DSP
Tools product line of JTAG emulators target board connector only. EMU has a
22.5 k
internal pull-up resistor.
Core Power Supply
. Nominally +1.2 V dc and supplies the DSP’s core processor
(13 pins on the BGA package, 32 pins on the LQFP package).
I/O Power Supply
. Nominally +3.3 V dc (6 pins on the BGA package, 10 pins on the
LQFP package).
Analog Power Supply
. Nominally +1.2 V dc and supplies the DSP’s internal PLL
(clock generator). This pin has the same specifications as V
DDINT
, except that added
filtering circuitry is required.
For more information, see Power Supplies on Page 8.
Analog Power Supply Return
.
Power Supply Return
.
(54 pins on the BGA package, 39 pins on the LQFP package).
XTAL
O
Output only
2
CLKCFG1–0
I
Input only
RSTOUT/CLKOUT
O
Output only
RESET
I/A
Input only
TCK
I
Input only
3
TMS
I/S
Three-state with
pull-up enabled
Three-state with
pull-up enabled
Three-state
4
Three-state with
pull-up enabled
TDI
I/S
TDO
TRST
O
I/A
EMU
O (O/D)
Three-state with
pull-up enabled
V
DDINT
P
V
DDEXT
P
A
VDD
P
A
VSS
GND
G
G
1
RD, WR, and ALE are continuously driven by the DSP and will not be three-stated.
2
Output only is a three-state driver with its output path always enabled.
3
Input only is a three-state driver, with both output path and pull-up disabled.
4
Three-state is a three-state driver, with pull-up disabled.
Table 2. Pin Descriptions (Continued)
Pin
Type
State During and
After Reset
Function
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相關代理商/技術參數 |
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|---|---|
| ADSP-21262SKATZ-200 | 制造商:Analog Devices 功能描述: |
| ADSP-21262SKBC-200 | 功能描述:IC DSP 32BIT 200MHZ 136-CSPBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - DSP（數字式信號處理器） 系列:SHARC® 標準包裝:2 系列:StarCore 類型:SC140 內核 接口:DSI，以太網，RS-232 時鐘速率:400MHz 非易失內存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，FCBGA 供應商設備封裝:431-FCPBGA（20x20） 包裝:托盤 |
| ADSP-21262SKBC200R | 制造商:Analog Devices 功能描述:DSP Floating-Point 32-Bit 200MHz 200MIPS 136-Pin CSP-BGA T/R |
| ADSP-21262SKBC-200X | 制造商:Analog Devices 功能描述: |
| ADSP-21262SKBCZ200 | 功能描述:IC DSP CTLR 32BIT 136CSPBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數字式信號處理器） 系列:SHARC® 標準包裝:40 系列:TMS320DM64x, DaVinci™ 類型:定點 接口:I²C，McASP，McBSP 時鐘速率:400MHz 非易失內存:外部 芯片上RAM:160kB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:0°C ~ 90°C 安裝類型:表面貼裝 封裝/外殼:548-BBGA，FCBGA 供應商設備封裝:548-FCBGA（27x27） 包裝:托盤 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
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