- 您現在的位置：買賣IC網 > PDF目錄374033 > ADSP-21262SKBC-200 (ANALOG DEVICES INC) SHARC Processor PDF資料下載
參數資料
| 型號： | ADSP-21262SKBC-200 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數字信號處理 |
| 英文描述： | SHARC Processor |
| 中文描述： | 16-BIT, 66.67 MHz, OTHER DSP, PBGA136 |
| 封裝： | MO-205AE, BGA-136 |
| 文件頁數： | 4/44頁 |
| 文件大小： | 1295K |
| 代理商： | ADSP-21262SKBC-200 |
第1頁第2頁第3頁當前第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁
Rev. A
|
Page 4 of 44
|
May 2004
ADSP-21262
GENERAL DESCRIPTION
The ADSP-21262 SHARC DSP is a member of the SIMD
SHARC family of DSPs featuring Analog Devices Super Har-
vard Architecture. The ADSP-21262 is source code compatible
with the ADSP-21160 and ADSP-21161 DSPs as well as with
first generation ADSP-2106x SHARC processors in SISD (Sin-
gle-Instruction, Single-Data) mode. Like other SHARC DSPs,
the ADSP-21262 is a 32-bit/40-bit floating-point processor opti-
mized for high precision signal processing applications with its
dual-ported on-chip SRAM, mask-programmable ROM, multi-
ple internal buses to eliminate I/O bottlenecks, and an
innovative Digital Audio Interface (DAI).
As shown in the functional block diagram
on Page 1
, the ADSP-
21262 uses two computational units to deliver a 5 to 10 times
performance increase over the ADSP-2106x on a range of DSP
algorithms. Fabricated in a state-of-the-art, high speed, CMOS
process, the ADSP-21262 DSP achieves an instruction cycle
time of 5 ns at 200 MHz. With its SIMD computational hard-
ware, the ADSP-21262 can perform 1200 MFLOPS running at
200 MHz.
Table 1
shows performance benchmarks for the ADSP-21262.
The ADSP-21262 continues SHARC’s industry leading stan-
dards of integration for DSPs, combining a high performance
32-bit DSP core with integrated, on-chip system features. These
features include 2 Mbits dual-ported SRAM memory, 4 Mbits
dual-ported ROM, an I/O processor that supports 22 DMA
channels, six serial ports, an SPI interface, external parallel bus,
and Digital Audio Interface (DAI).
The block diagram of the ADSP-21262
on Page 1
illustrates the
following architectural features:
Two processing elements, each containing an ALU, Multi-
plier, Shifter, and Data Register File
Data Address Generators (DAG1, DAG2)
Program sequencer with instruction cache
PM and DM buses capable of supporting four 32-bit data
transfers between memory and the core at every core pro-
cessor cycle
Three Programmable Interval Timers with PWM Genera-
tion, PWM Capture/Pulse Width Measurement, and
External Event Counter Capabilities
On-chip dual-ported SRAM (2M bits)
On-chip dual-ported mask-programmable ROM (4M bits)
JTAG test access port
The block diagram of the ADSP-21262 IOP
on Page 1
, illus-
trates the following architectural features:
8- or 16-bit parallel port that supports interfaces to off-chip
memory peripherals
DMA controller
Six full duplex serial ports
SPI compatible interface
Digital Audio Interface that includes two precision clock
generators (PCG), an input data port (IDP), six serial ports,
eight serial interfaces, a 20-bit synchronous parallel input
port, 10 interrupts, six flag outputs, six flag inputs, three
timers, and a flexible signal routing unit (SRU)
Figure 2 on Page 5
shows one sample configuration of a SPORT
using the precision clock generator to interface with an I
2
S ADC
and an I
2
S DAC with a much lower jitter clock than the serial
port would generate itself. Many other SRU configurations are
possible.
ADSP-21262 FAMILY CORE ARCHITECTURE
The ADSP-21262 is code compatible at the assembly level with
the ADSP-21266, ADSP-21160 and ADSP-21161, and with the
first generation ADSP-2106x SHARC DSPs. The ADSP-21262
shares architectural features with the ADSP-2126x and
ADSP-2116x SIMD SHARC family of DSPs, as detailed in the
following sections.
SIMD Computational Engine
The ADSP-21262 contains two computational processing ele-
ments that operate as a Single-Instruction Multiple-Data
(SIMD) engine. The processing elements are referred to as PEX
and PEY and each contains an ALU, multiplier, shifter, and reg-
ister file. PEX is always active, and PEY may be enabled by
setting the PEYEN mode bit in the MODE1 register. When this
mode is enabled, the same instruction is executed in both pro-
cessing elements, but each processing element operates on
different data. This architecture is efficient at executing math
intensive DSP algorithms.
Entering SIMD mode also has an effect on the way data is trans-
ferred between memory and the processing elements. When in
SIMD mode, twice the data bandwidth is required to sustain
computational operation in the processing elements. Because of
this requirement, entering SIMD mode also doubles the band-
width between memory and the processing elements. When
using the DAGs to transfer data in SIMD mode, two data values
are transferred with each access of memory or the register file.
Table 1. ADSP-21262 Benchmarks (at 200 MHz)
Benchmark Algorithm
Speed
(at 200 MHz)
46
μ
s
2.5 ns
10 ns
1024 Point Complex FFT (Radix 4, with reversal)
FIR Filter (per tap)
1
IIR Filter (per biquad)
1
Matrix Multiply (pipelined)
[3×3] × [3×1]
[4×4] × [4×1]
Divide (y/×)
Inverse Square Root
1
Assumes two files in multichannel SIMD mode
22.5 ns
40 ns
15 ns
22.5 ns
相關PDF資料 |
PDF描述 |
|---|---|
| ADSP-21262SKBCZ200 | SHARC Processor |
| ADSP-21266 | SHARC Embedded Processor |
| ADSP-21266SKBC-2B | SHARC Embedded Processor |
| ADSP-21266SKBCZ-2B | SHARC Embedded Processor |
| ADSP-21266SKBCZ-2C | SHARC Embedded Processor |
相關代理商/技術參數 |
參數描述 |
|---|---|
| ADSP-21262SKBC200R | 制造商:Analog Devices 功能描述:DSP Floating-Point 32-Bit 200MHz 200MIPS 136-Pin CSP-BGA T/R |
| ADSP-21262SKBC-200X | 制造商:Analog Devices 功能描述: |
| ADSP-21262SKBCZ200 | 功能描述:IC DSP CTLR 32BIT 136CSPBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數字式信號處理器） 系列:SHARC® 標準包裝:40 系列:TMS320DM64x, DaVinci™ 類型:定點 接口:I²C，McASP，McBSP 時鐘速率:400MHz 非易失內存:外部 芯片上RAM:160kB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:0°C ~ 90°C 安裝類型:表面貼裝 封裝/外殼:548-BBGA，FCBGA 供應商設備封裝:548-FCBGA（27x27） 包裝:托盤 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
| ADSP-21262SKBCZ200 | 制造商:Analog Devices 功能描述:DIGITAL SIGNAL PROCESSOR IC |
| ADSP21262SKBCZ200R | 功能描述:IC DSP CTLR 32BIT 136CSPBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數字式信號處理器） 系列:SHARC® 標準包裝:2 系列:StarCore 類型:SC140 內核 接口:DSI，以太網，RS-232 時鐘速率:400MHz 非易失內存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，FCBGA 供應商設備封裝:431-FCPBGA（20x20） 包裝:托盤 |
發布緊急采購，3分鐘左右您將得到回復。