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參數資料
| 型號： | ADSP-21262SKBC-200 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數字信號處理 |
| 英文描述： | SHARC Processor |
| 中文描述： | 16-BIT, 66.67 MHz, OTHER DSP, PBGA136 |
| 封裝： | MO-205AE, BGA-136 |
| 文件頁數： | 6/44頁 |
| 文件大小： | 1295K |
| 代理商： | ADSP-21262SKBC-200 |
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Rev. A
|
Page 6 of 44
|
May 2004
ADSP-21262
Fourier transforms. The two DAGs of the ADSP-21262 contain
sufficient registers to allow the creation of up to 32 circular buff-
ers (16 primary register sets, 16 secondary). The DAGs
automatically handle address pointer wraparound, reduce over-
head, increase performance, and simplify implementation.
Circular buffers can start and end at any memory location.
Flexible Instruction Set
The 48-bit instruction word accommodates a variety of parallel
operations for concise programming. For example, the
ADSP-21262 can conditionally execute a multiply, an add, and a
subtract in both processing elements while branching and fetch-
ing up to four 32-bit values from memory—all in a single
instruction.
ADSP-21262 MEMORY AND I/O INTERFACE
FEATURES
The ADSP-21262 adds the following architectural features to
the SIMD SHARC family core.
Dual-Ported On-Chip Memory
The ADSP-21262 contains two megabits of internal SRAM and
four megabits of internal mask-programmable ROM. Each
block can be configured for different combinations of code and
data storage (see
ADSP-21262 Memory Map on Page 7
). Each
memory block is dual-ported for single-cycle, independent
accesses by the core processor and I/O processor. The dual-
ported memory, in combination with three separate on-chip
buses, allows two data transfers from the core and one from the
I/O processor, in a single cycle.
The ADSP-21262’s SRAM can be configured as a maximum of
64K words of 32-bit data, 128K words of 16-bit data, 42K words
of 48-bit instructions (or 40-bit data), or combinations of differ-
ent word sizes up to two megabits. All of the memory can be
accessed as 16-bit, 32-bit, 48-bit, or 64-bit words. A 16-bit float-
ing-point storage format is supported that effectively doubles
the amount of data that may be stored on-chip. Conversion
between the 32-bit floating-point and 16-bit floating-point for-
mats is performed in a single instruction. While each memory
block can store combinations of code and data, accesses are
most efficient when one block stores data using the DM bus for
transfers, and the other block stores instructions and data using
the PM bus for transfers.
Using the DM bus and PM buses, with one dedicated to each
memory block assures single-cycle execution with two data
transfers. In this case, the instruction must be available in the
cache.
DMA Controller
The ADSP-21262’s on-chip DMA controller allows zero-over-
head data transfers without processor intervention. The DMA
controller operates independently and invisibly to the processor
core, allowing DMA operations to occur while the core is simul-
taneously executing its program instructions. DMA transfers
can occur between the ADSP-21262’s internal memory and its
serial ports, the SPI-compatible (Serial Peripheral Interface)
port, the IDP (Input Data Port), Parallel Data Acquisition Port
(PDAP), or the parallel port. Twenty-two channels of DMA are
available on the ADSP-21262—one for the SPI interface, 12 via
the serial ports, eight via the Input Data Port, and one via the
processor’s parallel port. Programs can be downloaded to the
ADSP-21262 using DMA transfers. Other DMA features
include interrupt generation upon completion of DMA trans-
fers, and DMA chaining for automatic linked DMA transfers.
Digital Audio Interface (DAI)
The Digital Audio Interface (DAI) provides the ability to con-
nect various peripherals to any of the DSPs 20 DAI pins
(DAI_P[20:1]).
Programs make these connections using the Signal Routing
Unit (SRU, shown in
Figure 1
).
The SRU is a matrix routing unit (or group of multiplexers) that
enables the peripherals provided by the DAI to be intercon-
nected under software control. This provides easy use of the
DAI associated peripherals for a much wider variety of applica-
tions by using a larger set of algorithms than is possible with
nonconfigurable signal paths.
The DAI also includes six serial ports, two precision clock gen-
erators (PCGs), an input data port (IDP), six flag outputs and
six flag inputs, and three timers. The IDP provides an additional
input path to the DSP core configurable as either eight channels
of I
2
S or serial data, or as seven channels plus a single 20-bit
wide synchronous parallel data acquisition port. Each data
channel has its own DMA channel that is independent from the
ADSP-21262's serial ports.
For complete information on using the DAI, see the
ADSP-2126x SHARC DSP Peripherals Manual
.
Serial Ports
The ADSP-21262 features six synchronous serial ports that pro-
vide an inexpensive interface to a wide variety of digital and
mixed-signal peripheral devices such as Analog Devices
AD183x family of audio codecs, DACs, or ADCs. The serial
ports are made up of two data lines, a clock, and frame sync. The
data lines can be programmed to either transmit or receive and
each data line has its own dedicated DMA channel.
Serial ports are enabled via 12 programmable and simultaneous
receive or transmit pins that support up to 24 transmit or 24
receive channels of serial data when all six SPORTs are enabled,
or six full duplex TDM streams of 128 channels per frame.
The serial ports operate at up to one-quarter of the DSP core
clock rate, providing each with a maximum data rate of
50M bits/s for a 200 MHz core. Serial port data can be automat-
ically transferred to and from on-chip memory via dedicated
DMA channels. Each of the serial ports can work in conjunction
with another serial port to provide TDM support. One SPORT
provides two transmit signals while the other SPORT provides
the two receive signals. The frame sync and clock are shared.
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| ADSP-21266SKBCZ-2B | SHARC Embedded Processor |
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相關代理商/技術參數 |
參數描述 |
|---|---|
| ADSP-21262SKBC200R | 制造商:Analog Devices 功能描述:DSP Floating-Point 32-Bit 200MHz 200MIPS 136-Pin CSP-BGA T/R |
| ADSP-21262SKBC-200X | 制造商:Analog Devices 功能描述: |
| ADSP-21262SKBCZ200 | 功能描述:IC DSP CTLR 32BIT 136CSPBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數字式信號處理器） 系列:SHARC® 標準包裝:40 系列:TMS320DM64x, DaVinci™ 類型:定點 接口:I²C，McASP，McBSP 時鐘速率:400MHz 非易失內存:外部 芯片上RAM:160kB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:0°C ~ 90°C 安裝類型:表面貼裝 封裝/外殼:548-BBGA，FCBGA 供應商設備封裝:548-FCBGA（27x27） 包裝:托盤 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
| ADSP-21262SKBCZ200 | 制造商:Analog Devices 功能描述:DIGITAL SIGNAL PROCESSOR IC |
| ADSP21262SKBCZ200R | 功能描述:IC DSP CTLR 32BIT 136CSPBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數字式信號處理器） 系列:SHARC® 標準包裝:2 系列:StarCore 類型:SC140 內核 接口:DSI，以太網，RS-232 時鐘速率:400MHz 非易失內存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，FCBGA 供應商設備封裝:431-FCPBGA（20x20） 包裝:托盤 |
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