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參數(shù)資料
| 型號： | ADSP-21262SKBC-200 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | SHARC Processor |
| 中文描述： | 16-BIT, 66.67 MHz, OTHER DSP, PBGA136 |
| 封裝： | MO-205AE, BGA-136 |
| 文件頁數(shù)： | 5/44頁 |
| 文件大小： | 1295K |
| 代理商： | ADSP-21262SKBC-200 |
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ADSP-21262
Rev. A
|
Page 5 of 44
|
May 2004
Independent, Parallel Computation Units
Within each processing element is a set of computational units.
The computational units consist of an arithmetic/logic unit
(ALU), multiplier, and shifter. These units perform all opera-
tions in a single cycle. The three units within each processing
element are arranged in parallel, maximizing computational
throughput. Single multifunction instructions execute parallel
ALU and multiplier operations. In SIMD mode, the parallel
ALU and multiplier operations occur in both processing ele-
ments. These computation units support IEEE 32-bit single-
precision floating-point, 40-bit extended precision floating-
point, and 32-bit fixed-point data formats.
Data Register File
A general-purpose data register file is contained in each
processing element. The register files transfer data between the
computation units and the data buses, and store intermediate
results. These 10-port, 32-register (16 primary, 16 secondary)
register files, combined with the ADSP-2126x enhanced Har-
vard architecture, allow unconstrained data flow between
computation units and internal memory. The registers in PEX
are referred to as R0-R15 and in PEY as S0-S15.
Single-Cycle Fetch of Instruction and Four Operands
The ADSP-21262 features an enhanced Harvard architecture in
which the data memory (DM) bus transfers data and the pro-
gram memory (PM) bus transfers both instructions and data
(see
Figure 1 on Page 1
). With the ADSP-21262’s separate pro-
gram and data memory buses and on-chip instruction cache,
the processor can simultaneously fetch four operands (two over
each data bus) and one instruction (from the cache), all in a sin-
gle cycle.
Instruction Cache
The ADSP-21262 includes an on-chip instruction cache that
enables three-bus operation for fetching an instruction and four
data values. The cache is selective—only the instructions whose
fetches conflict with PM bus data accesses are cached. This
cache allows full-speed execution of core, looped operations
such as digital filter multiply-accumulates, and FFT butterfly
processing.
Data Address Generators with Zero-Overhead Hardware
Circular Buffer Support
The ADSP-21262’s two data address generators (DAGs) are
used for indirect addressing and implementing circular data
buffers in hardware. Circular buffers allow efficient program-
ming of delay lines and other data structures required in digital
signal processing, and are commonly used in digital filters and
Figure 2. ADSP-21262 System Sample Configuration
DAI
SPORT5
SPORT4
SPORT3
SPORT2
SPORT0
SCLK0
SFS0
SD0A
SD0B
SRU
DAI_P1
DAI_P2
DAI_P3
DAI_P18
DAI_P19
DAI_P20
DAC
(OPTIONAL)
ADC
(OPTIONAL)
FS
CLK
SDAT
FS
CLK
SDAT
3
CLOCK
FLAG3-1
2
2
CLKIN
XTAL
CLK_CFG1-0
BOOTCFG1-0
ADDR
PARALLEL
PORT
RAM, ROM
BOOT ROM
I/O DEVICE
OE
WE
DATA
RD
WR
CLKOUT
ALE
AD15-0
LATCH
RESET
JTAG
6
ADSP-21262
A
D
C
CS
FLAG0
PCGB
PCGA
CLK
FS
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| ADSP-21262SKBCZ200 | SHARC Processor |
| ADSP-21266 | SHARC Embedded Processor |
| ADSP-21266SKBC-2B | SHARC Embedded Processor |
| ADSP-21266SKBCZ-2B | SHARC Embedded Processor |
| ADSP-21266SKBCZ-2C | SHARC Embedded Processor |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADSP-21262SKBC200R | 制造商:Analog Devices 功能描述:DSP Floating-Point 32-Bit 200MHz 200MIPS 136-Pin CSP-BGA T/R |
| ADSP-21262SKBC-200X | 制造商:Analog Devices 功能描述: |
| ADSP-21262SKBCZ200 | 功能描述:IC DSP CTLR 32BIT 136CSPBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:SHARC® 標準包裝:40 系列:TMS320DM64x, DaVinci™ 類型:定點 接口:I²C，McASP，McBSP 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:160kB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:0°C ~ 90°C 安裝類型:表面貼裝 封裝/外殼:548-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:548-FCBGA（27x27） 包裝:托盤 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
| ADSP-21262SKBCZ200 | 制造商:Analog Devices 功能描述:DIGITAL SIGNAL PROCESSOR IC |
| ADSP21262SKBCZ200R | 功能描述:IC DSP CTLR 32BIT 136CSPBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:SHARC® 標準包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤 |
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