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參數資料
| 型號： | ADSP-21262SKSTZ200 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數字信號處理 |
| 英文描述： | SHARC Processor |
| 中文描述： | 16-BIT, 66.67 MHz, OTHER DSP, PQFP144 |
| 封裝： | LEAD FREE, MS-026BFB, LQFP-144 |
| 文件頁數： | 2/44頁 |
| 文件大小： | 1295K |
| 代理商： | ADSP-21262SKSTZ200 |
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Rev. A
|
Page 2 of 44
|
May 2004
ADSP-21262
KEY FEATURES
At 200 MHz (5 ns) core instruction rate, the ADSP-21262
operates at 1200 MFLOPS peak/800 MFLOPS sustained
performance whether operating on fixed or floating point
data
400 MMACS sustained performance at 200 MHz
Super Harvard Architecture—three independent buses for
dual data fetch, instruction fetch, and nonintrusive, zero-
overhead I/O
2M bits on-chip dual-ported SRAM (1M bit block 0, 1M bit
block 1) for simultaneous access by core processor and
DMA
4M bits on-chip dual-ported mask-programmable ROM
(2M bits in block 0 and 2M bits in block 1)
Dual data address generators (DAGs) with modulo and bit-
reverse addressing
Zero-overhead looping with single-cycle loop setup, provid-
ing efficient program sequencing
Single instruction multiple data (SIMD) architecture
provides:
Two computational processing elements
Concurrent execution— Each processing element executes
the same instruction, but operates on different data
Parallelism in buses and computational units allows: Sin-
gle cycle executions (with or without SIMD) of a multiply
operation; an ALU operation; a dual memory read or
write; and an instruction fetch
Transfers between memory and core at up to four 32-bit
floating- or fixed-point words per cycle, sustained
2.4G Bytes/s bandwidth at 200 MHz core instruction rate.
In addition, 900M Bytes/sec is available via DMA
Accelerated FFT butterfly computation through a multiply
with add and subtract instruction
DMA controller supports:
22 zero-overhead DMA channels for transfers between
ADSP-21262 internal memory and serial ports (12), the
input data port (IDP) (8), SPI-compatible port (1), and the
parallel port (1)
32-bit background DMA transfers at core clock speed, in par-
allel with full-speed processor execution
Asynchronous parallel/external port provides:
Access to asynchronous external memory
16 multiplexed address/data lines support 24-bit address
external address range with 8-bit data or 16-bit address
external address range with 16-bit data
66M Byte per sec transfer rate for 200 MHz core rate
256 word page boundaries
External memory access in a dedicated DMA channel
8- to 32-bit and 16- to 32-bit word packing options
Programmable wait state options: 2 to 31 CCLK
Digital audio interface (DAI) includes six serial ports, two pre-
cision clock generators, an input data port, three
programmable timers and a signal routing unit
Serial ports provide:
Six dual data line serial ports that operate at up to 50 Mbits/s
for a 200 MHz core on each data line — each has a clock,
frame sync, and two data lines that can be configured as
either a receiver or transmitter pair
Left-justified sample pair and I
2
S support, programmable
direction for up to 24 simultaneous receive or transmit
channels using two I
2
S compatible stereo devices per serial
port
TDM support for telecommunications interfaces including
128 TDM channel support for telephony interfaces such as
H.100/H.110
Up to 12 TDM stream support, each with 128 channels per
frame
Companding selection on a per channel basis in TDM mode
Input data port provides an additional input path to the DSP
core configurable as either eight channels of I
2
S or serial
data or as seven channels plus a single 20-bit wide syn-
chronous parallel data acquisition port
Supports receive audio channel data in I
2
S, left-justified
sample pair, or right-justified mode
Signal routing unit provides configurable and flexible
connections between all DAI components, six serial ports,
an input data port, two precision clock generators, three
timers, 10 interrupts, six flag inputs, six flag outputs, and
20 SRU I/O pins (DAI_Px)
Serial peripheral interface (SPI)
Master or slave serial boot through SPI
Full-duplex operation
Master-slave mode multimaster support
Open drain outputs
Programmable baud rates, clock polarities, and phases
3 Muxed Flag/IRQ lines
1 Muxed Flag/Timer expired line
ROM based security features:
JTAG access to memory permitted with a 64-bit key
Protected memory regions that can be assigned to limit
access under program control to sensitive code
PLL has a wide variety of software and hardware multi-
plier/divider ratios
JTAG background telemetry for enhanced emulation
features
IEEE 1149.1 JTAG standard test access port and on-chip
emulation
Dual voltage: 3.3 V I/O, 1.2 V core
Available in 136-ball BGA and 144-lead LQFP packages
Lead free packages are also available
相關PDF資料 |
PDF描述 |
|---|---|
| ADSP-21262 | SHARC Processor |
| ADSP-21262SKBC-200 | SHARC Processor |
| ADSP-21262SKBCZ200 | SHARC Processor |
| ADSP-21266 | SHARC Embedded Processor |
| ADSP-21266SKBC-2B | SHARC Embedded Processor |
相關代理商/技術參數 |
參數描述 |
|---|---|
| ADSP-21262SKSTZ200 | 制造商:Analog Devices 功能描述:IC 32-BIT DSP |
| ADSP-21266 | 制造商:AD 制造商全稱:Analog Devices 功能描述:SHARC Embedded Processor |
| ADSP-21266_07 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Embedded Processor |
| ADSP-21266KSTZ-1C | 制造商:Analog Devices 功能描述:- Trays |
| ADSP-21266KSTZ-2C | 制造商:Analog Devices 功能描述:- Trays |
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