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參數資料
| 型號： | ADSP-21365SBBC-ENG |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數字信號處理 |
| 英文描述： | SHARC Processor |
| 中文描述： | 16-BIT, 55.55 MHz, OTHER DSP, PBGA136 |
| 封裝： | MO-205AE, MBGA-136 |
| 文件頁數： | 25/54頁 |
| 文件大小： | 559K |
| 代理商： | ADSP-21365SBBC-ENG |
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ADSP-21365/6
Preliminary Technical Data
Rev. PrA
|
Page 25 of 54
|
September 2004
Memory Read—Parallel Port
Use these specifications for asynchronous interfacing to memo-
ries (and memory-mapped peripherals) when the
ADSP-21365/6 is accessing external memory space.
Table 20. 8-Bit Memory Read Cycle
Parameter
Timing Requirements
t
DRS
t
DRH
t
DAD
Min
Max
Unit
Address/Data 7–0 Setup Before RD High
Address/Data 7–0 Hold After RD High
Address 15–8 to Data Valid
3.3
0
ns
ns
ns
D + t
PCLK
– 5
Switching Characteristics
t
ALEW
t
ADAS
1
t
RRH
t
ALERW
t
RWALE
t
ADAH
1
t
ALEHZ
1
t
RW
t
RDDRV
t
ADRH
D = (Data Cycle Duration = the value set by the PPDUR bits (5–1) in the PPCTL register) × t
PCLK
H = t
PCLK
(if a hold cycle is specified, else H = 0)
F = 7 x t
PCLK
(if FLASH_MODE is set else F = 0)
t
PCLK
= (Peripheral) Clock Period = 2 × t
CCLK
1
On reset, ALE is an active high cycle. However, it can be configured by software to be active low.
ALE Pulse Width
Address/Data 15–0 Setup Before ALE Deasserted
Delay Between RD Rising Edge to Next Falling Edge.
ALE Deasserted to Read Asserted
Read Deasserted to ALE Asserted
Address/Data 15–0 Hold After ALE Deasserted
ALE Deasserted to Address/Data7–0 in High Z
RD Pulse Width
RD Address Drive After Read High
Address/Data 15–8 Hold After RD High
2 × t
PCLK
– 2.0
t
PCLK
– 2.5
H + t
PCLK
– 1
2 × t
PCLK
– 2
F + H + 0.5
t
PCLK
– 0.8
t
PCLK
– 0.8
D – 2
F + H + t
PCLK
– 1
H
ns
ns
ns
ns
ns
t
PCLK
ns
ns
ns
ns
Figure 17. Read Cycle For 8-Bit Memory Timing
VALID ADDRESS
VALID
ADDRESS
AD15-8
t
ADAS
VALID ADDRESS
AD7-0
t
ALEW
ALE
RD
t
RW
WR
t
ADAH
t
ADRH
t
DRS
t
DRH
t
DAD
t
ALERW
t
RWALE
VALID
DATA
VALID
ADDRESS
t
RDDRV
t
ALEHZ
VALID ADDRESS
VALID ADDRESS
VALID
DATA
t
RRH
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| ADSP-21365SBBCZENG | SHARC Processor |
| ADSP-21365SBSQ-ENG | SHARC Processor |
| ADSP-21365SKBCZENG | SHARC Processor |
| ADSP-21365SKSQZENG | SHARC Processor |
| ADSP-21366SKBCZENG | SHARC Processor |
相關代理商/技術參數 |
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|---|---|
| ADSP-21365SBBCZENG | 制造商:AD 制造商全稱:Analog Devices 功能描述:SHARC Processor |
| ADSP-21365SBSQ-ENG | 制造商:AD 制造商全稱:Analog Devices 功能描述:SHARC Processor |
| ADSP-21365SBSQZENG | 制造商:AD 制造商全稱:Analog Devices 功能描述:SHARC Processor |
| ADSP-21365SCSQ-ENG | 制造商:AD 制造商全稱:Analog Devices 功能描述:SHARC Processor |
| ADSP-21365SCSQZENG | 制造商:AD 制造商全稱:Analog Devices 功能描述:SHARC Processor |
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