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參數資料
| 型號： | ADSP-21365SBBC-ENG |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數字信號處理 |
| 英文描述： | SHARC Processor |
| 中文描述： | 16-BIT, 55.55 MHz, OTHER DSP, PBGA136 |
| 封裝： | MO-205AE, MBGA-136 |
| 文件頁數： | 4/54頁 |
| 文件大小： | 559K |
| 代理商： | ADSP-21365SBBC-ENG |
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Rev. PrA
|
Page 4 of 54
|
September 2004
ADSP-21365/6
Preliminary Technical Data
Independent, Parallel Computation Units
Within each processing element is a set of computational units.
The computational units consist of an arithmetic/logic unit
(ALU), multiplier, and shifter. These units perform all opera-
tions in a single cycle. The three units within each processing
element are arranged in parallel, maximizing computational
throughput. Single multifunction instructions execute parallel
ALU and multiplier operations. In SIMD mode, the parallel
ALU and multiplier operations occur in both processing ele-
ments. These computation units support IEEE 32-bit single-
precision floating-point, 40-bit extended precision floating-
point, and 32-bit fixed-point data formats.
Data Register File
A general-purpose data register file is contained in each pro-
cessing element. The register files transfer data between the
computation units and the data buses, and store intermediate
results. These 10-port, 32-register (16 primary, 16 secondary)
register files, combined with the ADSP-2136x enhanced Har-
vard architecture, allow unconstrained data flow between
computation units and internal memory. The registers in PEX
are referred to as R0-R15 and in PEY as S0-S15.
Single-Cycle Fetch of Instruction and Four Operands
The ADSP-21365/6 features an enhanced Harvard architecture
in which the data memory (DM) bus transfers data and the pro-
gram memory (PM) bus transfers both instructions and data
(see
Figure 1 on page 1
). With the ADSP-21365/6’s separate
program and data memory buses and on-chip instruction cache,
the processor can simultaneously fetch four operands (two over
each data bus) and one instruction (from the cache), all in a sin-
gle cycle.
Instruction Cache
The ADSP-21365/6 includes an on-chip instruction cache that
enables three-bus operation for fetching an instruction and four
data values. The cache is selective—only the instructions whose
fetches conflict with PM bus data accesses are cached. This
cache allows full-speed execution of core, looped operations
such as digital filter multiply-accumulates, and FFT butterfly
processing.
Data Address Generators With Zero-Overhead Hardware
Circular Buffer Support
The ADSP-21365/6’s two data address generators (DAGs) are
used for indirect addressing and implementing circular data
buffers in hardware. Circular buffers allow efficient program-
ming of delay lines and other data structures required in digital
Figure 2. ADSP-21365/6 System Sample Configuration
DAI
SPI
IDP
SRC
SPDIF
SPORT0-5
TIMERS
SCLK0
SFS0
SD0A
SD0B
SRU
DAI_P1
DAI_P2
DAI_P3
DAI_P18
DAI_P19
DAI_P20
DAC
(OPTIONAL)
ADC
(OPTIONAL)
FS
CLK
SDAT
FS
CLK
SDAT
3
CLOCK
FLAG3-1
2
2
CLKIN
XTAL
CLK_CFG1-0
BOOTCFG1-0
ADDR
PARALLEL
PORT
RAM, ROM
BOOT ROM
I/O DEVICE
OE
WE
CS
DATA
RD
WR
CLKOUT
ALE
AD15-0
LATCH
RESET
JTAG
6
ADSP-21365/6
A
D
C
FLAG0
PCGB
PCGA
CLK
FS
相關PDF資料 |
PDF描述 |
|---|---|
| ADSP-21365SBBCZENG | SHARC Processor |
| ADSP-21365SBSQ-ENG | SHARC Processor |
| ADSP-21365SKBCZENG | SHARC Processor |
| ADSP-21365SKSQZENG | SHARC Processor |
| ADSP-21366SKBCZENG | SHARC Processor |
相關代理商/技術參數 |
參數描述 |
|---|---|
| ADSP-21365SBBCZENG | 制造商:AD 制造商全稱:Analog Devices 功能描述:SHARC Processor |
| ADSP-21365SBSQ-ENG | 制造商:AD 制造商全稱:Analog Devices 功能描述:SHARC Processor |
| ADSP-21365SBSQZENG | 制造商:AD 制造商全稱:Analog Devices 功能描述:SHARC Processor |
| ADSP-21365SCSQ-ENG | 制造商:AD 制造商全稱:Analog Devices 功能描述:SHARC Processor |
| ADSP-21365SCSQZENG | 制造商:AD 制造商全稱:Analog Devices 功能描述:SHARC Processor |
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