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參數(shù)資料
型號: ADSP-21365SCSQ-ENG
廠商: ANALOG DEVICES INC
元件分類: 數(shù)字信號處理
英文描述: SHARC Processor
中文描述: 16-BIT, 55.55 MHz, OTHER DSP, PQFP144
封裝: MS-026BFB-HD, HSLQFP-144
文件頁數(shù): 28/54頁
文件大?。?/td> 559K
代理商: ADSP-21365SCSQ-ENG
Rev. PrA
|
Page 28 of 54
|
September 2004
ADSP-21365/6
Preliminary Technical Data
Table 23. 16-bit Memory Write Cycle
Parameter
Switching Characteristics
t
ALEW
t
ADAS
1
t
ALERW
t
RWALE
t
WRH
t
ADAH
1
t
WW
t
ALEHZ
1
t
DWS
t
DWH
D = (Data Cycle Duration = the value set by the PPDUR bits (5–1) in the PPCTL register) × t
PCLK
H = t
PCLK
(if a hold cycle is specified, else H = 0)
F = 7 x t
PCLK
(if FLASH_MODE is set else F = 0)
1
On reset, ALE is an active high cycle. However, it can be configured by software to be active low.
Min
Max
Unit
ALE Pulse Width
Address/Data 15–0 Setup Before ALE Deasserted
ALE Deasserted to Write Asserted
Write Deasserted to ALE Asserted
Delay Between WR Rising Edge to next WR Falling Edge
Address/Data 15–0 Hold After ALE Deasserted
WR Pulse Width
ALE Deasserted to Address/Data15–0 in High Z
Address/Data 15–0 Setup Before WR High
Address/Data 15–0 Hold After WR High
2 × t
PCLK
– 2
t
PCLK
– 2.5
2 × t
PCLK
– 2
H + 0.5
F + H + t
PCLK
– 2
t
PCLK
– 0.5
D – F – 2
t
PCLK
– 1.5
D – F + t
PCLK
– 4
H
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Figure 20. Write Cycle For 16-Bit Memory Timing
AD15-0
VALID
ADDRESS
VALID DATA
t
ADAS
ALE
RD
WR
t
ADAH
t
WRH
t
RWALE
t
ALEW
t
ALERW
t
WW
t
DWS
t
DWH
VALID DATA
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