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參數資料
| 型號： | ADSP-21366SKSQZENG |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數字信號處理 |
| 英文描述： | SHARC Processor |
| 中文描述： | 16-BIT, 55.55 MHz, OTHER DSP, PQFP144 |
| 封裝： | LEAD FREE, MS-026BFB-HD, HSLQFP-144 |
| 文件頁數： | 29/54頁 |
| 文件大?。?/td> | 559K |
| 代理商： | ADSP-21366SKSQZENG |
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ADSP-21365/6
Preliminary Technical Data
Rev. PrA
|
Page 29 of 54
|
September 2004
Serial Ports
To determine whether communication is possible between two
devices at clock speed n, the following specifications must be
confirmed: 1) frame sync delay and frame sync setup and hold,
2) data delay and data setup and hold, and 3) SCLK width.
Serial port signals (SCLK, FS, data channel A,/data channel B)
are routed to the DAI_P20–1 pins using the SRU. Therefore, the
timing specifications provided below are valid at the
DAI_P20–1 pins.
Table 24. Serial Ports—External Clock
Parameter
Timing Requirements
t
SFSE
1
Min
Max
Unit
FS Setup Before SCLK
(Externally Generated FS in either Transmit or Receive Mode)
FS Hold After SCLK
(Externally Generated FS in either Transmit or Receive Mode)
Receive Data Setup Before Receive SCLK
Receive Data Hold After SCLK
SCLK Width
SCLK Period
2.5
ns
t
HFSE
1
2.5
2.5
2.5
24
48
ns
ns
ns
ns
ns
t
SDRE
1
t
HDRE
1
t
SCLKW
t
SCLK
Switching Characteristics
t
DFSE
2
FS Delay After SCLK
(Internally Generated FS in either Transmit or Receive Mode)
FS Hold After SCLK
(Internally Generated FS in either Transmit or Receive Mode)
Transmit Data Delay After Transmit SCLK
Transmit Data Hold After Transmit SCLK
7
ns
t
HOFSE
2
2
ns
ns
ns
t
DDTE
2
t
HDTE
2
1
Referenced to sample edge.
2
Referenced to drive edge.
7
2
Table 25. Serial Ports—Internal Clock
Parameter
Timing Requirements
t
SFSI
1
Min
Max
Unit
FS Setup Before SCLK
(Externally Generated FS in either Transmit or Receive Mode)
FS Hold After SCLK
(Externally Generated FS in either Transmit or Receive Mode)
Receive Data Setup Before SCLK
Receive Data Hold After SCLK
7
ns
t
HFSI
1
2.5
7
2.5
ns
ns
ns
t
SDRI
1
t
HDRI
1
Switching Characteristics
t
DFSI
2
t
HOFSI
2
t
DFSI
2
t
HOFSI
2
t
DDTI
2
t
HDTI
2
t
SCLKIW
1
Referenced to the sample edge.
2
Referenced to drive edge.
FS Delay After SCLK (Internally Generated FS in Transmit Mode)
FS Hold After SCLK (Internally Generated FS in Transmit Mode)
FS Delay After SCLK (Internally Generated FS in Receive or Mode)
FS Hold After SCLK (Internally Generated FS in Receive Mode)
Transmit Data Delay After SCLK
Transmit Data Hold After SCLK
Transmit or Receive SCLK Width
3
ns
ns
ns
ns
ns
ns
ns
–1.0
3
–1.0
3
–1.0
0.5t
SCLK
– 2
0.5t
SCLK
+ 2
相關PDF資料 |
PDF描述 |
|---|---|
| ADSP-21365SKSQ-ENG | SHARC Processor |
| ADSP-21366SBSQ-ENG | SHARC Processor |
| ADSP-21366SCSQ-ENG | SHARC Processor |
| ADSP-21366 | Cap-Free, NMOS, 150mA Low Dropout Regulator with Reverse Current Protection |
| ADSP-21366SKBC-ENG | Cap-Free, NMOS, 150mA Low Dropout Regulator with Reverse Current Protection |
相關代理商/技術參數 |
參數描述 |
|---|---|
| ADSP-21366WBBCZ-1A | 制造商:AD 制造商全稱:Analog Devices 功能描述:SHARC Processor |
| ADSP-21366YSWZ-2AA | 功能描述:IC DSP 32BIT 200MHZ EPAD 144LQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數字式信號處理器） 系列:SHARC® 標準包裝:2 系列:StarCore 類型:SC140 內核 接口:DSI，以太網，RS-232 時鐘速率:400MHz 非易失內存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，FCBGA 供應商設備封裝:431-FCPBGA（20x20） 包裝:托盤 |
| ADSP-21367 | 制造商:AD 制造商全稱:Analog Devices 功能描述:SHARC Processors |
| ADSP-21367_06 | 制造商:AD 制造商全稱:Analog Devices 功能描述:SHARC Processors |
| ADSP-21367_08 | 制造商:AD 制造商全稱:Analog Devices 功能描述:SHARC Processors |
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