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參數資料
| 型號： | ADSP-2163BS-100 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數字信號處理 |
| 英文描述： | 100V 1A ULTRA FAST LOW-LOSS CONTROLLED AVALANCHE RECTIFIER, SMA US1 SERIES, DO- |
| 中文描述： | 24-BIT, 25 MHz, OTHER DSP, PQFP80 |
| 封裝： | METRIC, PLASTIC, QFP-80 |
| 文件頁數： | 28/39頁 |
| 文件大小： | 243K |
| 代理商： | ADSP-2163BS-100 |
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ADSP-216x
–28–
TIMING PARAMETERS (ADSP-2162/ADSP-2164/ADSP-2166)
GENERAL NOTES
Use the exact timing information given. Do not attempt to de-
rive parameters from the addition or subtraction of others. While
addition or subtraction would yield meaningful results for an
individual device, the values given in this data sheet reflect sta-
tistical variations and worst cases. Consequently, you cannot
meaningfully add parameters to derive longer times.
TIMING NOTES
Switching Characteristics
specify how the processor changes its
signals. You have no control over this timing—circuitry external
to the processor must be designed for compatibility with these
signal characteristics. Switching characteristics tell you what the
processor will do in a given circumstance. You can also use
switching characteristics to ensure that any timing requirement
of a device connected to the processor (such as memory) is
satisfied.
Timing Requirements
apply to signals that are controlled by cir-
cuitry external to the processor, such as the data input for a read
operation. Timing requirements guarantee that the processor
operates correctly with other devices.
MEMORY REQUIREMENTS
The table below shows common memory device specifications
and the corresponding ADSP-216x timing parameters, for your
convenience.
ADSP-216x
Timing Parameter
Memory Device Specification
Timing Parameter Definition
Address Setup to Write Start
Address Setup to Write End
Address Hold Time
Data Setup Time
Data Hold Time
OE
to Data Valid
Address Access Time
t
ASW
t
AW
t
WRA
t
DW
t
DH
t
RDD
t
AA
A0–A13,
DMS
,
PMS
Setup Before
WR
Low
A0–A13,
DMS
,
PMS
Setup Before
WR
Deasserted
A0–A13,
DMS
,
PMS
Hold After
WR
Deasserted
Data Setup Before
WR
High
Data Hold After
WR
High
RD
Low to Data Valid
A0–A13,
DMS
,
PMS
,
BMS
to Data Valid
相關PDF資料 |
PDF描述 |
|---|---|
| ADSP-2163BS-66 | DSP Microcomputers with ROM |
| ADSP-2163KS-100 | DSP Microcomputers with ROM |
| ADSP-2163KS-66 | DSP Microcomputers with ROM |
| ADSP-2164BS-40 | SWITCH SLIDE DP3T RT ANG L=6MM |
| ADSP-2164KS-40 | DSP Microcomputers with ROM |
相關代理商/技術參數 |
參數描述 |
|---|---|
| ADSP-2163BS-1002 | 制造商:AD 制造商全稱:Analog Devices 功能描述:ADSP-2100 Family DSP Microcomputers |
| ADSP-2163BS-66 | 制造商:AD 制造商全稱:Analog Devices 功能描述:ADSP-2100 Family DSP Microcomputers |
| ADSP-2163BS-662 | 制造商:AD 制造商全稱:Analog Devices 功能描述:ADSP-2100 Family DSP Microcomputers |
| ADSP-2163KP-100 | 制造商:AD 制造商全稱:Analog Devices 功能描述:ADSP-2100 Family DSP Microcomputers |
| ADSP-2163KP-1002 | 制造商:AD 制造商全稱:Analog Devices 功能描述:ADSP-2100 Family DSP Microcomputers |
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