- 您現在的位置：買賣IC網 > PDF目錄374037 > ADSP-2195MBCA-140X (ANALOG DEVICES INC) LM2991 Negative Low Dropout Adjustable Regulator; Package: CERDIP; No of Pins: 16; Container: Rail PDF資料下載
參數資料
| 型號： | ADSP-2195MBCA-140X |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數字信號處理 |
| 英文描述： | LM2991 Negative Low Dropout Adjustable Regulator; Package: CERDIP; No of Pins: 16; Container: Rail |
| 中文描述： | 16-BIT, 160 MHz, OTHER DSP, PBGA144 |
| 封裝： | MINI, BGA-144 |
| 文件頁數： | 13/68頁 |
| 文件大小： | 951K |
| 代理商： | ADSP-2195MBCA-140X |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁當前第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁
This information applies to a product under development. Its characteristics and specifications are subject to change with-
out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
13
REV. PrA
For current information contact Analog Devices at 800/262-5643
ADSP-2195
September 2001
page 11
and
Clock Signals on page 14
. Ten mem-
ory-mapped registers control operation of the
Programmable Flag pins:
Flag Direction register
Specifies the direction of each individual PFx pin as input
or output.
Flag Control and Status registers
Specify the value to drive on each individual PFx output
pin. As input, software can predicate instruction
execution on the value of individual PFx input pins
captured in this register. One register sets bits, and one
register clears bits.
Flag Interrupt Mask registers
Enable and disable each individual PFx pin to function
as an interrupt to the DSP’s core. One register sets bits to
enable interrupt function, and one register clears bits to
disable interrupt function. Input PFx pins function as
hardware interrupts, and output PFx pins function as
software interrupts—latching in the IMASK and IRPTL
registers.
Flag Interrupt Polarity register
Specifies the polarity (active high or low) for interrupt
sensitivity on each individual PFx pin.
Flag Sensitivity registers
Specify whether individual PFx pins are level- or
edge-sensitive and specify—if edge-sensitive—whether
just the rising edge or both the rising and falling edges of
the signal are significant. One register selects the type of
sensitivity, and one register selects which edges are signif-
icant for edge-sensitivity.
Low Power Operation
The ADSP-2195 has four low-power options that signifi-
cantly reduce the power dissipation when the device
operates under standby conditions. To enter any of these
modes, the DSP executes an IDLE instruction. The
ADSP-2195 uses configuration of the PDWN, STOPCK,
and STOPALL bits in the PLLCTL register to select
between the low-power modes as the DSP executes the
IDLE. Depending on the mode, an IDLE shuts off clocks
to different parts of the DSP in the different modes. The
low power modes are:
Idle
Power-Down Core
Power-Down Core/Peripherals
Power-Down All
Idle Mode
When the ADSP-2195 is in Idle mode, the DSP core stops
executing instructions, retains the contents of the instruc-
tion pipeline, and waits for an interrupt. The core clock and
peripheral clock continue running.
To enter Idle mode, the DSP can execute the IDLE instruc-
tion anywhere in code. To exit Idle mode, the DSP responds
to an interrupt and (after two cycles of latency) resumes
executing instructions with the instruction after the IDLE.
Power-down Core Mode
When the ADSP-2195 is in Power-Down Core mode, the
DSP core clock is off, but the DSP retains the contents of
the pipeline and keeps the PLL running. The peripheral bus
keeps running, letting the peripherals receive data.
To enter Power-Down Core mode, the DSP executes an
IDLE instruction after performing the following tasks:
Enter a power-down interrupt service routine
Check for pending interrupts and I/O service routines
Clear (= 0) the PDWN bit in the PLLCTL register
Clear (= 0) the STOPALL bit in the PLLCTL register
Set (= 1) the STOPCK bit in the PLLCTL register
To exit Power-Down Core mode, the DSP responds to an
interrupt and (after two cycles of latency) resumes executing
instructions with the instruction after the IDLE.
Power-Down Core/Peripherals Mode
When the ADSP-2195 is in Power-Down Core/Peripherals
mode, the DSP core clock and peripheral bus clock are off,
but the DSP keeps the PLL running. The DSP does not
retain the contents of the instruction pipeline.The periph-
eral bus is stopped, so the peripherals cannot receive data.
To enter Power-Down Core/Peripherals mode, the DSP
executes an IDLE instruction after performing the
following tasks:
Enter a power-down interrupt service routine
Check for pending interrupts and I/O service routines
Clear (= 0) the PDWN bit in the PLLCTL register
Set (= 1) the STOPALL bit in the PLLCTL register
To exit Power-Down Core/Peripherals mode, the DSP
responds to an interrupt and (after five to six cycles of
latency) resumes executing instructions with the instruction
after the IDLE.
Power-Down All Mode
When the ADSP-2195 is in Power-Down All mode, the
DSP core clock, the peripheral clock, and the PLL are all
stopped. The DSP does not retain the contents of the
instruction pipeline. The peripheral bus is stopped, so the
peripherals cannot receive data.
To enter Power-Down All mode, the DSP executes an IDLE
instruction after performing the following tasks:
Enter a power-down interrupt service routine
Check for pending interrupts and I/O service routines
Set (= 1) the PDWN bit in the PLLCTL register
相關PDF資料 |
PDF描述 |
|---|---|
| ADSP-2195MKST-160X | LM2991 Negative Low Dropout Adjustable Regulator; Package: TO-263; No of Pins: 5; Qty per Container: 45; Container: Rail |
| ADSP-2196 | DSP Microcomputer |
| ADSP-2196MBCA-140X | DSP Microcomputer |
| ADSP-2196MBST-140X | DSP Microcomputer |
| ADSP-2196MKCA-160X | DSP Microcomputer |
相關代理商/技術參數 |
參數描述 |
|---|---|
| ADSP-2195MBST-140 | 功能描述:IC DSP CONTROLLER 16BIT 144LQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - DSP（數字式信號處理器） 系列:ADSP-21xx 標準包裝:40 系列:TMS320DM64x, DaVinci™ 類型:定點 接口:I²C，McASP，McBSP 時鐘速率:400MHz 非易失內存:外部 芯片上RAM:160kB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:0°C ~ 90°C 安裝類型:表面貼裝 封裝/外殼:548-BBGA，FCBGA 供應商設備封裝:548-FCBGA（27x27） 包裝:托盤 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
| ADSP-2195MKCA-160 | 制造商:Analog Devices 功能描述:DSP Fixed-Point 24-Bit 160MHz 160MIPS 144-Pin CSP-BGA 制造商:Rochester Electronics LLC 功能描述:16-BIT,160 MIPS, 2.5V, 80KBYTES RAM - Bulk |
| ADSP-2195MKST-160 | 制造商:Analog Devices 功能描述:DSP Fixed-Point 24-Bit 160MHz 160MIPS 144-Pin LQFP 制造商:Analog Devices 功能描述:IC MICROCOMPUTER 16-BIT |
| adsp-2196mbca-140 | 制造商:Analog Devices 功能描述: |
| adsp-2196mbst-140 | 制造商:Analog Devices 功能描述:DSP Fixed-Point 16-Bit 140MHz 140MIPS 144-Pin LQFP 制造商:Rochester Electronics LLC 功能描述: |
發布緊急采購，3分鐘左右您將得到回復。