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參數資料
| 型號： | ADSP-2195MBCA-140X |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數字信號處理 |
| 英文描述： | LM2991 Negative Low Dropout Adjustable Regulator; Package: CERDIP; No of Pins: 16; Container: Rail |
| 中文描述： | 16-BIT, 160 MHz, OTHER DSP, PBGA144 |
| 封裝： | MINI, BGA-144 |
| 文件頁數： | 40/68頁 |
| 文件大小： | 951K |
| 代理商： | ADSP-2195MBCA-140X |
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For current information contact Analog Devices at 800/262-5643
ADSP-2195
September 2001
This information applies to a product under development. Its characteristics and specifications are subject to change with-
out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
40
REV. PrA
Host Port ACC Mode Read Cycle Timing
Table 17
and
Figure 20
describe host port read operations in Address Cycle Control (ACC) mode. For more information
on ACK, Ready, ALE, and ACC mode selection, see the Host port modes description
on page 10
.
Table 17. Host Port ACC Mode Read Cycle Timing
Parameter
Description
Min
Max
Unit
Switching Characteristics
t
RHKS
HRD asserted to HACK asserted (setup, ACK Mode)
1
1+t
NH
1
1
t
are peripheral bus latencies (n
the same time.
t
HCLK
); these are internal DSP latencies related to the number of peripherals attempting to access DSP memory at
ns
t
RHKH
HRD de-asserted to HACK de-asserted (hold, ACK Mode)
2
ns
t
RHS
HRD asserted to HACK asserted (setup, Ready Mode)
1
ns
t
RHH
HRD asserted to HACK de-asserted (hold, Ready Mode)
2+t
NH
1
ns
Timing Requirements
t
CSAL
HCMS or HCIOMS asserted to HALE asserted (delay)
0
ns
t
ALCS
HALE de-asserted to optional HCMS or HCIOMS
de-asserted
1
ns
t
RCSW
HRD de-asserted to HCMS or HCIOMS de-asserted
1
ns
t
ALW
HALE asserted to HWR asserted
0.5
ns
t
ALER
HALE de-asserted to HWR asserted
1
ns
t
CSR
HCMS or HCIOMS asserted to HRD asserted
1
2
ns
t
RCS
HRD de-asserted (after last byte) to HCMS or
HCIOMS de-asserted (ready for next read)
1
ns
t
WAL
HWR de-asserted to HALE de-asserted (delay)
1.5
ns
t
HKRD
HACK asserted to HRD de-asserted (hold, ACK Mode)
1.5
ns
t
ADW
Address valid to HWR de-asserted (setup)
4
ns
t
WAD
HWR de-asserted to address invalid (hold)
1
ns
t
RDH
HRD de-asserted to data invalid (hold)
1
ns
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| ADSP-2195MKCA-160 | 制造商:Analog Devices 功能描述:DSP Fixed-Point 24-Bit 160MHz 160MIPS 144-Pin CSP-BGA 制造商:Rochester Electronics LLC 功能描述:16-BIT,160 MIPS, 2.5V, 80KBYTES RAM - Bulk |
| ADSP-2195MKST-160 | 制造商:Analog Devices 功能描述:DSP Fixed-Point 24-Bit 160MHz 160MIPS 144-Pin LQFP 制造商:Analog Devices 功能描述:IC MICROCOMPUTER 16-BIT |
| adsp-2196mbca-140 | 制造商:Analog Devices 功能描述: |
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