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參數(shù)資料
| 型號(hào)： | ADSP-2195MBST-140X |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | DSP Microcomputer |
| 中文描述： | 16-BIT, 160 MHz, OTHER DSP, PQFP144 |
| 封裝： | METRIC, PLASTIC, LQFP-144 |
| 文件頁數(shù)： | 12/68頁 |
| 文件大小： | 951K |
| 代理商： | ADSP-2195MBST-140X |
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For current information contact Analog Devices at 800/262-5643
ADSP-2195
During transfers, the SPI ports simultaneously transmit and
receive by serially shifting data in and out on their two serial
data lines. The serial clock line synchronizes the shifting and
sampling of data on the two serial data lines.
In master mode, the DSP’s core performs the following
sequence to set up and initiate SPI transfers:
1.
Enables and configures the SPI port’s operation (data
size, and transfer format).
2.
Selects the target SPI slave with an SPIxSELy output
pin (reconfigured Programmable Flag pin).
3.
Defines one or more DMA descriptors in Page 0 of I/O
memory space (optional in DMA mode only).
4.
Enables the SPI DMA engine and specifies transfer
direction (optional in DMA mode only).
5.
In non-DMA mode only, reads or writes the SPI port
receive or transmit data buffer.
The SCKx line generates the programmed clock pulses
for simultaneously shifting data out on MOSIx and
shifting data in on MISOx. In DMA mode only, transfers
continue until the SPI DMA word count transitions
from 1 to 0.
In slave mode, the DSP’s core performs the following
sequence to set up the SPI port to receive data from a master
transmitter:
1.
Enables and configures the SPI slave port to match the
operation parameters set up on the master (data size
and transfer format) SPI transmitter.
2.
Defines and generates a receive DMA descriptor in
Page 0 of memory space to interrupt at the end of the
data transfer (optional in DMA mode only).
3.
Enables the SPI DMA engine for a receive access
(optional in DMA mode only).
4.
Starts receiving the data on the appropriate SPI SCKx
edges after receiving an SPI chip select on an SPISSx
input pin (reconfigured Programmable Flag pin)
from a master
In DMA mode only, reception continues until the SPI
DMA word count transitions from 1 to 0. The DSP’s core
could continue, by queuing up the next DMA descriptor.
A slave mode transmit operation is similar, except the DSP’s
core specifies the data buffer in memory space from which
to transmit data, generates and relinquishes control of the
transmit DMA descriptor, and begins filling the SPI port’s
data buffer. If the SPI controller isn’t ready on time to
transmit, it can transmit a “zero” word.
September 2001
This information applies to a product under development. Its characteristics and specifications are subject to change with-
out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
12
REV. PrA
UART Port
The UART port provides a simplified UART interface to
another peripheral or Host. It performs full duplex, asyn-
chronous transfers of serial data. Options for the UART
include support for 5–8 data bits; 1 or 2 stop bits; and none,
even, or odd parity. The UART port supports two modes
of operation:
PIO (programmed I/O)
The DSP’s core sends or receives data by writing or
reading I/O-mapped UATX or UARX registers, respec-
tively. The data is double-buffered on both transmit and
receive.
DMA (direct memory access)
The DMA controller transfers both transmit and receive
data. This reduces the number and frequency of inter-
rupts required to transfer data to and from memory. The
UART has two dedicated DMA channels. These DMA
channels have lower priority than most DMA channels
because of their relatively low service rates.
The UART’s baud rate (see
Figure 5
), serial data format,
error code generation and status, and interrupts are
programmable:
Supported bit rates range from 95 bits to 6.25M bits per
second (100 MHz peripheral clock).
Supported data formats are 7- or 12-bit frames.
Transmit and receive status can be configured to generate
maskable interrupts to the DSP’s core.
The timers can be used to provide a hardware-assisted
autobaud detection mechanism for the UART interface.
Programmable Flag (PFx) Pins
The ADSP-2195 has 16 bidirectional, general-purpose I/O,
Programmable Flag (PF15–0) pins. The PF7–0 pins are
dedicated to general-purpose I/O. The PF15–8 pins serve
either as general-purpose I/O pins (if the DSP is connected
to an 8-bit external data bus) or serve as DATA15–8 lines
(if the DSP is connected to a 16-bit external data bus). The
Programmable Flag pins have special functions for clock
multiplier selection and for SPI port operation. For more
information, see
Serial Peripheral Interface (SPI) Ports on
Figure 5. UART Clock Rate Calculation
1
1
Where D = 1 to 65536
UART Clock Rate
16
D
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相關(guān)PDF資料 |
PDF描述 |
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| ADSP-2195 | LM2991 Negative Low Dropout Adjustable Regulator; Package: CERDIP; No of Pins: 16; Qty per Container: 25; Container: Rail |
| ADSP-2195MBCA-140X | LM2991 Negative Low Dropout Adjustable Regulator; Package: CERDIP; No of Pins: 16; Container: Rail |
| ADSP-2195MKST-160X | LM2991 Negative Low Dropout Adjustable Regulator; Package: TO-263; No of Pins: 5; Qty per Container: 45; Container: Rail |
| ADSP-2196 | DSP Microcomputer |
| ADSP-2196MBCA-140X | DSP Microcomputer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADSP-2195MKCA-160 | 制造商:Analog Devices 功能描述:DSP Fixed-Point 24-Bit 160MHz 160MIPS 144-Pin CSP-BGA 制造商:Rochester Electronics LLC 功能描述:16-BIT,160 MIPS, 2.5V, 80KBYTES RAM - Bulk |
| ADSP-2195MKST-160 | 制造商:Analog Devices 功能描述:DSP Fixed-Point 24-Bit 160MHz 160MIPS 144-Pin LQFP 制造商:Analog Devices 功能描述:IC MICROCOMPUTER 16-BIT |
| adsp-2196mbca-140 | 制造商:Analog Devices 功能描述: |
| adsp-2196mbst-140 | 制造商:Analog Devices 功能描述:DSP Fixed-Point 16-Bit 140MHz 140MIPS 144-Pin LQFP 制造商:Rochester Electronics LLC 功能描述: |
| ADSP-2196MBST-140Z | 制造商:Analog Devices 功能描述:DSP Fixed-Point 16-Bit 140MHz 140MIPS 144-Pin LQFP |
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