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參數資料
型號: ADSP-BF532SBBC400
廠商: ANALOG DEVICES INC
元件分類: 數字信號處理
英文描述: Blackfin Embedded Processor
中文描述: 16-BIT, 40 MHz, OTHER DSP, PBGA160
封裝: MO-205AE, CSBGA-160
文件頁數: 28/56頁
文件大小: 671K
代理商: ADSP-BF532SBBC400
Rev. 0
|
Page 28 of 56
|
March 2004
ADSP-BF531/ADSP-BF532/ADSP-BF533
Serial Ports
Table 21
through
Table 26 on Page 29
and
Figure 16 on Page 30
through
Figure 18 on Page 32
describe Serial Port operations.
Table 21. Serial Ports—External Clock
Parameter
Timing Requirements
t
SFSE
t
HFSE
t
SDRE
t
HDRE
t
SCLKEW
t
SCLKE
1
Referenced to sample edge.
Min
Max
Unit
TFS/RFS Setup Before TSCLK/RSCLK
1
TFS/RFS Hold After TSCLK/RSCLK
1
Receive Data Setup Before RSCLK
1
Receive Data Hold After RSCLK
1
TSCLK/RSCLK Width
TSCLK/RSCLK Period
3.0
3.0
3.0
3.0
4.5
15.0
ns
ns
ns
ns
ns
ns
Table 22. Serial Ports—Internal Clock
Parameter
Timing Requirements
t
SFSI
t
HFSI
t
SDRI
t
HDRI
t
SCLKEW
t
SCLKE
1
Referenced to sample edge.
Min
Max
Unit
TFS/RFS Setup Before TSCLK/RSCLK
1
TFS/RFS Hold After TSCLK/RSCLK
1
Receive Data Setup Before RSCLK
1
Receive Data Hold After RSCLK
1
TSCLK/RSCLK Width
TSCLK/RSCLK Period
8.0
–2.0
6.0
0.0
4.5
15.0
ns
ns
ns
ns
ns
ns
Table 23. Serial Ports—External Clock
Parameter
Switching Characteristics
t
DFSE
t
HOFSE
t
DDTE
t
HDTE
1
Referenced to drive edge.
Min
Max
Unit
TFS/RFS Delay After TSCLK/RSCLK (Internally Generated TFS/RFS)
1
TFS/RFS Hold After TSCLK/RSCLK (Internally Generated TFS/RFS)
1
Transmit Data Delay After TSCLK
1
Transmit Data Hold After TSCLK
1
10.0
ns
ns
ns
ns
0.0
10.0
0.0
Table 24. Serial Ports—Internal Clock
Parameter
Switching Characteristics
t
DFS
I
t
HOFS
I
t
DDT
I
t
HDT
I
t
SCLKIW
1
Referenced to drive edge.
Min
Max
Unit
TFS/RFS Delay After TSCLK/RSCLK (Internally Generated TFS/RFS)
1
TFS/RFS Hold After TSCLK/RSCLK (Internally Generated TFS/RFS)
1
Transmit Data Delay After TSCLK
1
Transmit Data Hold After TSCLK
1
TSCLK/RSCLK Width
3.0
ns
ns
ns
ns
ns
1.0
3.0
2.0
4.5
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