
ADSP-BF531/ADSP-BF532/ADSP-BF533
Rev. 0
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Page 5 of 56
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March 2004
Figure 2. Blackfin Processor Core
SP
FP
P5
P4
P3
P2
P1
P0
SEQUENCER
ALIGN
DECODE
LOOP BUFFER
DAG0
DAG1
16
16
8
8
8
8
40
40
A0
A1
BARREL
SHIFTER
DATA ARITHMETIC UNIT
CONTROL
UNIT
ADDRESS ARITHMETIC UNIT
I3
I2
I1
I0
L3
L2
L1
L0
B3
B2
B1
B0
M3
M2
M1
M0
LD0 32 BITS
LD1 32 BITS
SD 32 BITS
R7.L
R6.L
R5.L
R4.L
R3.L
R2.L
R1.L
R0.L
R7.H
R6.H
R5.H
R4.H
R3.H
R2.H
R1.H
R0.H
R7
R6
R5
R4
R3
R2
R1
R0
Figure 3. ADSP-BF533 Internal/External Memory Map
RESERVED
CORE MMR REGISTERS (2M BYTE)
RESERVED
SCRATCHPAD SRAM (4K BYTE)
INSTRUCTION SRAM (64K BYTE)
SYSTEM MMR REGISTERS (2M BYTE)
RESERVED
RESERVED
DATA BANK B SRAM / CACHE (16K BYTE)
DATA BANK B SRAM (16K BYTE)
DATA BANK A SRAM / CACHE (16K BYTE)
ASYNC MEMORY BANK 3 (1M BYTE)
ASYNC MEMORY BANK 2 (1M BYTE)
ASYNC MEMORY BANK 1 (1M BYTE)
ASYNC MEMORY BANK 0 (1M BYTE)
SDRAM MEMORY (16M BYTE TO 128M BYTE)
INSTRUCTION SRAM / CACHE (16K BYTE)
I
E
0xFFFF FFFF
0xFFE0 0000
0xFFB0 0000
0xFFA1 4000
0xFFA1 0000
0xFF90 8000
0xFF90 4000
0xFF80 8000
0xFF80 4000
0xEF00 0000
0x2040 0000
0x2030 0000
0x2020 0000
0x2010 0000
0x2000 0000
0x0800 0000
0x0000 0000
0xFFC0 0000
0xFFB0 1000
0xFFA0 0000
RESERVED
RESERVED
DATA BANK A SRAM (16K BYTE)
0xFF90 0000
0xFF80 0000
RESERVED
Figure 4. ADSP-BF532 Internal/External Memory Map
CORE MMR REGISTERS (2M BYTE)
RESERVED
SCRATCHPAD SRAM(4K BYTE)
SYSTEM MMR REGISTERS (2M BYTE)
RESERVED
RESERVED
DATA BANK B SRAM / CACHE (16K BYTE)
RESERVED
DATA BANK A SRAM / CACHE (16K BYTE)
ASYNC MEMORY BANK 3 (1M BYTE)
ASYNC MEMORY BANK 2 (1M BYTE)
ASYNC MEMORY BANK 1 (1M BYTE)
ASYNC MEMORY BANK 0 (1M BYTE)
SDRAMMEMORY (16M BYTE TO 128M BYTE)
INSTRUCTION SRAM / CACHE (16K BYTE)
I
E
0xFFFF FFFF
0xFFE0 0000
0xFFB0 0000
0xFFA1 4000
0xFFA0 8000
0xFF90 8000
0xFF90 4000
0xFF80 8000
0xFF80 4000
0xEF00 0000
0x2040 0000
0x2030 0000
0x2020 0000
0x2010 0000
0x2000 0000
0x0800 0000
0x0000 0000
0xFFC0 0000
0xFFB0 1000
0xFFA0 0000
RESERVED
RESERVED
RESERVED
0xFFA1 0000
INSTRUCTION SRAM (32K BYTE)
RESERVED