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參數資料
型號: ADSP2186
廠商: Analog Devices, Inc.
元件分類: 數字信號處理
英文描述: DSP Microcomputer
中文描述: DSP微機
文件頁數: 19/32頁
文件大小: 293K
代理商: ADSP2186
ADSP-2186
REV. 0
–19–
Parameter
Min
Max
Unit
Bus Request/Grant
Timing Requirements
:
t
BH
t
BS
BR
Hold after CLK OUT High
1
BR
Setup before CLK OUT Low
1
0.25 t
CK
+ 2
0.25 t
CK
+ 17
ns
ns
Switching Characteristics
:
t
SD
t
SDB
t
SE
t
SEC
t
SDBH
t
SEH
CLK OUT High to
xMS
,
RD
,
WR
Disable
xMS
,
RD
,
WR
Disable to
BG
Low
BG
High to
xMS
,
RD
,
WR
Enable
xMS
,
RD
,
WR
Enable to CLK OUT High
xMS
,
RD
,
WR
Disable to
BGH
Low
2
BGH
High to
xMS
,
RD
,
WR
Enable
2
0.25 t
CK
+ 10
ns
ns
ns
ns
ns
ns
0
0
0.25 t
CK
– 7
0
0
NOT ES
xMS
=
PMS
,
DMS
,
CMS
,
IOMS
,
BMS
.
1
BR
is an asynchronous signal. If
BR
meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise the signal will be recognized on
the following cycle. Refer to the
ADSP-2100 Family User’s Manual
for
BR
/
BG
cycle relationships.
2
BGH
is asserted when the bus is granted and the processor requires control of the bus to continue.
CLKOUT
t
SD
t
SDB
t
SE
t
SEC
t
SDBH
t
SEH
t
BS
BR
t
BH
CLKOUT
PMS
,
DMS
BMS
,
RD
WR
BG
BGH
Figure 16. Bus Request–Bus Grant
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