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參數資料
| 型號： | ADUC7021BCP62 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Precision Analog Microcontroller 12-bit Analog I/O, ARM7TDMI MCU |
| 中文描述： | 32-BIT, FLASH, 45.5 MHz, MICROCONTROLLER, QCC40 |
| 封裝： | 6 X 6 MM, MO-220VJJD-2, LFCSP-40 |
| 文件頁數： | 62/80頁 |
| 文件大?。?/td> | 840K |
| 代理商： | ADUC7021BCP62 |
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ADuC702x Series
Preliminary Technical Data
PROGRAMMABLE LOGIC ARRAY (PLA)
Rev. PrB | Page 62 of 80
The ADuC702x integrates a fully Programmable Logic Array
(PLA) which consists of two independent but interconnected
PLA blocks. Each block consists of eight PLA elements, which
gives a total of 16 PLA elements.
A PLA element contains a two-input lookup table that can be
configured to generate any logic output function based on two
inputs and a flip-flop as represented in Figure 27 below.
0
1
2
3
4
LOOK-UP
TABLE
A
B
Figure 27: PLA element
In total, 30 GPIO pins are available on the ADuC702x for the
PLA. These include 16 input pins and 14 output pins. They need
to be configured in the GPxCON register as PLA pins before
using the PLA. Note that the comparator output is also included
as one of the 16 input pins.
The PLA is configured via a set of user MMRs and the output(s)
of the PLA can be routed to the internal interrupt system, to the
CONV
START
signal of the ADC, to a MMR or to any of the 16
PLA output pins.
The interconnection between the two blocks is supported by
connecting output of element 7 of block 1 fed back to the input
0 of mux 0 of element 0 of block 0, and the output of element 7
of block 0 is fed back to the input 0 of mux 0 of element 0 of
block 1.
PLA Block 0
Element
Input
Output
0
P1.0
P1.7
1
P1.1
P0.4
2
P1.2
P0.5
3
P1.3
P0.6
4
P1.4
P0.7
5
P1.5
P2.0
6
P1.6
P2.1
7
P0.0
P2.2
PLA Block 1
Input
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
Element
8
9
10
11
12
13
14
15
Output
P4.0
P4.1
P4.2
P4.3
P4.4
P4.5
P4.6
P4.7
Table 51: element input/output
PLA MMRs interface
The PLA peripheral interface consists on 21 MMRs:
-
PLAELMx
: element0 to element 15 control registers,
configure the input and output mux of each element, select
the function in the lookup table and bypass/use the flip-flop.
-
PLACLK
: clock selection for the flip-flops of block 0 and
clock selection for the flip-flops of block 1
-
PLAIRQ
: enable IRQ0 or/and IRQ1 and select the source of
the IRQ
-
PLAADC
: PLA source fro ADC start conversion signal
-
PLADIN
: data input MMR for PLA
-
PLADOUT
: data output MMR for PLA. This register is
always updated.
A PLA tool is provided in the development system to easily
configure the PLA.
Table 52: PLAELMx MMR Bit Descriptions
Description PLAELM0 PLAELM1 - 7 PLAELM8 PLAELM9-15
Reserved
00 – element 15 element 0 element 7 element 8
01 – element 2 element 2 element 10 element 10
10 – element 4 element 4 element 12 element 12
11 – element 6 element 6 element 14 element 14
00 – element 1 element 1 element 9 element 9
01 – element 3 element 3 element 11 element 11
10 – element 5 element 5 element 13 element 13
11 – element 7 element 7 element 15 element 15
Mux (2) control
Set
by user to select the output of mux (1)
Cleared
by user to select the bit value from PLADIN
Mux (3) control
Set
by user to select the input pin of the particular element
Cleared
by user to select the output of mux (0)
0000 – 0
0001 – NOR
0010 – B AND NOT A
Bit
31-11
10-9
Mux (0) control, select feedback from:
8-7
Mux (1) control, select feedback from:
6
5
4-1
Look-up table control
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