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參數資料
| 型號： | ADUC814ARU |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MicroConverter, Small Package 12-Bit ADC with Embedded Flash MCU |
| 中文描述： | 8-BIT, FLASH, 16.78 MHz, MICROCONTROLLER, PDSO28 |
| 封裝： | 4.40 X 9.70 MM, MO-153AE, TSSOP-28 |
| 文件頁數： | 42/72頁 |
| 文件大小： | 846K |
| 代理商： | ADUC814ARU |
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ADuC814
POWER SUPPLY MONITOR
As its name suggests, the power supply monitor, once enabled,
monitors the supply (DV
DD
) on the ADuC814. It indicates when
any of the supply pins drop below one of four user-selectable
voltage trip points from 2.63 V to 4.63 V. For correct operation
of the power supply monitor function, DV
DD
must be equal to
or greater than 2.7 V. Monitor function is controlled via the
PSMCON SFR. If enabled via the IEIP2 SFR, the monitor
interrupts the core using the PSMI bit in the PSMCON SFR.
PSMCON
Power Supply Monitor Control Register
SFR Address
DFH
Power-On Default
DEH
Bit Addressable
No
Rev. A | Page 42 of 72
This bit is not cleared until the failing power supply has
returned above the trip point for at least 250 ms. This monitor
function allows the user to save working registers to avoid
possible data loss due to the low supply condition, and also
ensures that normal code execution does not resume until a safe
supply level is well established. The supply monitor is also
protected against spurious glitches triggering the interrupt
circuit.
----
CMPD
PSMI
TPD1
TPD0
----
----
PSMEN
Table 16. PSMCON SFR Bit Designations
Bit No.
Name
7
PSMCON.7
6
CMPD
Description
Reserved.
DV
DD
Comparator Bit.
This is a read-only bit and directly reflects the state of the DV
DD
comparator.
Read 1 indicates that the DV
DD
supply is above its selected trip point.
Read 0 indicates that the DV
DD
supply is below its selected trip point.
Power Supply Monitor Interrupt Bit.
This bit is set high by the MicroConverter if CMPD is low, indicating low digital supply. The PSMI bit can be used to
interrupt the processor. Once CMPD returns and remains high, a 250 ms counter is started. When this counter
times out, the PSMI interrupt is cleared. PSMI can also be written by the user; however, if the comparator output is
low, it is not possible for the user to clear PSMI.
DV
DD
Trip Point Selection Bits.
These bits select the DV
DD
trip-point voltage as follows:
TPD1
TPD0
Selected DV
DD
Trip Point (V)
0
0
4.63
0
1
3.08
1
0
2.93
1
1
2.63
Reserved.
Reserved.
Power Supply Monitor Enable Bit.
Set to 1 by the user to enable the power supply monitor circuit.
Cleared to 0 by the user to disable the power supply monitor circuit.
5
PSMI
4
3
TPD1
TPD0
2
1
0
PSMCON.2
PSMCON.1
PSMEN
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