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參數(shù)資料
| 型號(hào)： | ADUC814ARU |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MicroConverter, Small Package 12-Bit ADC with Embedded Flash MCU |
| 中文描述： | 8-BIT, FLASH, 16.78 MHz, MICROCONTROLLER, PDSO28 |
| 封裝： | 4.40 X 9.70 MM, MO-153AE, TSSOP-28 |
| 文件頁(yè)數(shù)： | 43/72頁(yè) |
| 文件大小： | 846K |
| 代理商： | ADUC814ARU |
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ADuC814
ADuC814 CONFIGURATION REGISTER (CFG814)
The ADuC814 is housed in a 28-lead TSSOP package. To
maintain as much functional compatibility with other
MicroConverter products, some pins share multiple I/O
functionality. Switching between these functions is controlled
via the ADuC814 configuration SFR, CFG814, located at SFR
address 9CH. A summary of these functions is described and a
detailed bit designation for the CFG814 SFR is given in Table 17.
Serial Peripheral Interface
The SPI interface on the ADuC814 shares the same pins as
digital outputs P3.5, P3.6, and P3.7. The SPE bit in SPICON is
used to select which interface is active at any one time. This is
described in greater detail in the next section. By default, these
pins operate as standard Port 3 pins. Bit 0 of the CFG814 SFR
must be set to 1 to enable the SPI interface on these Port 3 pins.
Rev. A | Page 43 of 72
External Clock
The ADuC814 is intended for use with a 32.768 kHz watch
crystal. The on-chip PLL locks onto a multiple of this to provide
a stable 16.777216 MHz clock for the device. On the ADuC814,
P3.5 alternate functions include T1 input and slave select in SPI
master mode. P3.5 also functions as external clock input, EXTCLK,
selected via Bit 1 of the CFG814 SFR. When selected, this
external clock bypasses the PLL and is used as the clock for the
device, therefore allowing the ADuC814 to be synchronized to
the rest of the application system. The maximum input frequency
of this external clock is 16.777216 MHz. If selected, the EXTCLK
signal affects the timing of the majority of peripherals on the
ADuC814 including the ADC, EEPROM controller, watchdog
timer, SPI interface clock, and the MicroConverter core clock.
CFG814
ADuC814 Configuration Register
SFR Address
9CH
Power-On Default
04H
Bit Addressable
No
EXTCLK
SER_EN
Table 17. CFG814 SFR Bit Designations
Bit No.
Name
1
EXTCLK
Description
External Clock Selection Bit.
Set to 1 to enable EXTCLK as MCU core clock.
Cleared to 0 to enable XTAL and PLL as the MCU core clock.
Serial Interface Enable Bit.
Set to 1 by the user to enable the SPI interface onto the P3.5, P3.6, and P3.7 pins.
Cleared to 0 by the user to enable standard Port 3 functionality on the P3.5, P3.6, and P3.7 pins.
0
SER_EN
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