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| 型號(hào)： | ADUC824BS |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MicroConverter, Dual-Channel 16-/24-Bit ADCs with Embedded FLASH MCU |
| 中文描述： | 8-BIT, FLASH, 12.58 MHz, MICROCONTROLLER, PQFP52 |
| 封裝： | PLASTIC, MQFP-52 |
| 文件頁(yè)數(shù)： | 25/68頁(yè) |
| 文件大小： | 1060K |
| 代理商： | ADUC824BS |
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REV. B
ADuC824
–25–
SFR INTERFACE TO THE PRIMARY AND AUXILIARY
ADCS
Both ADCs are controlled and configured via a number of SFRs
that are mentioned here and described in more detail in the
following pages.
ADCSTAT:
ADC Status Register. Holds general status of
the Primary and Auxiliary ADCs.
ADCMODE: ADC Mode Register. Controls general modes
of operation for Primary and Auxiliary ADCs.
ADC0CON:
Primary ADC Control Register. Controls
specific configuration of Primary ADC.
ADC1CON:
Auxiliary ADC Control Register. Controls
specific configuration of Auxiliary ADC.
SF:
Sinc Filter Register. Configures the decimation
factor for the Sinc3 filter and thus the Primary
and Auxiliary ADC update rates.
ICON:
Current Source Control Register. Allows user
control of the various on-chip current source
options.
ADC0L/M/H: Primary ADC 24-bit conversion result held in
these three 8-bit registers.
ADC1L/H:
Auxiliary ADC 16-bit conversion result held
in these two 8-bit registers.
OF0L/M/H:
Primary ADC 24-bit Offset Calibration Coefficient
held in these three 8-bit registers.
OF1L/H:
Auxiliary ADC 16-bit Offset Calibration Coefficient
held in these two 8-bit registers.
GN0L/M/H:
Primary ADC 24-bit Gain Calibration Coefficient
held in these three 8-bit registers.
GN1L/H:
Auxiliary ADC 16-bit Gain Calibration Coefficient
held in these two 8-bit registers.
ADCSTAT—(ADC Status Register)
This SFR reflects the status of both ADCs including data ready, calibration and various (ADC-related) error and warning conditions
including reference detect and conversion overflow/underflow flags.
SFR Address
D8H
Power-On Default Value
00H
Bit Addressable
Yes
0
Y
D
R
1
Y
D
R
L
A
C
F
E
R
X
O
N
0
R
R
E
1
R
R
E
—
—
Table III. ADCSTAT SFR Bit Designations
Bit
Name
Description
7
RDY0
Ready Bit for Primary ADC
Set
by hardware on completion of ADC conversion or calibration cycle.
Cleared
directly by the user or indirectly by write to the mode bits to start another Primary
ADC conversion or calibration. The Primary ADC is inhibited from writing further results to its
data or calibration registers until the RDY0 bit is cleared.
Ready Bit for Auxiliary ADC
Same definition as RDY0 referred to the Auxiliary ADC.
Calibration Status Bit
Set
by hardware on completion of calibration.
Cleared
indirectly by a write to the mode bits to start another ADC conversion or calibration.
No External Reference Bit
(only active if Primary or Auxiliary ADC is active).
Set
to indicate that one or both of the REFIN pins is floating or the applied voltage is below a
specified threshold. When Set conversion results are clamped to all ones,if using ext. reference.
Cleared
to indicate valid V
REF
.
Primary ADC Error Bit
Set
by hardware to indicate that the result written to the Primary ADC data registers has
been clamped to all zeros or all ones. After a calibration this bit also flags error conditions that
caused the calibration registers not to be written.
Cleared
by a write to the mode bits to initiate a conversion or calibration.
Auxiliary ADC Error Bit
Same definition as ERR0 referred to the Auxiliary ADC.
Reserved for Future Use
Reserved for Future Use
6
RDY1
5
CAL
4
NOXREF
3
ERR0
2
ERR1
1
0
—
—
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