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| 型號(hào)： | ADUC824BS |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MicroConverter, Dual-Channel 16-/24-Bit ADCs with Embedded FLASH MCU |
| 中文描述： | 8-BIT, FLASH, 12.58 MHz, MICROCONTROLLER, PQFP52 |
| 封裝： | PLASTIC, MQFP-52 |
| 文件頁(yè)數(shù)： | 61/68頁(yè) |
| 文件大小： | 1060K |
| 代理商： | ADUC824BS |
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REV. B
ADuC824
–61–
IEIP2
SFR Address
Power-On Default Value
Bit Addressable
Secondary Interrupt Enable and Priority Register
A9H
A0H
No
—
I
T
P
M
S
P
P
I
S
P
—
I
T
E
M
S
P
E
I
S
E
Table XXXII. IEIP2 SFR Bit Designations
Bit
Name
Description
7
6
5
4
3
2
1
0
—
PTI
PPSM
PSI
—
ETI
EPSM
ESI
Reserved for Future Use
Written by User to Select TIC Interrupt Priority (‘1’ = High; ‘0’ = Low).
Written by User to Select Power Supply Monitor Interrupt Priority (‘1’ = High; ‘0’ = Low).
Written by User to Select SPI/I
2
C Serial Port Interrupt Priority (‘1’ = High; ‘0’ = Low).
Reserved, This Bit Must Be ‘0.’
Written by User to Enable ‘1’ or Disable ‘0’ TIC Interrupt.
Written by User to Enable ‘1’ or Disable ‘0’ Power Supply Monitor Interrupt.
Written by User to Enable ‘1’ or Disable ‘0’ SPI/I
2
C Serial Port Interrupt.
Interrupt Priority
The Interrupt Enable registers are written by the user to enable
individual interrupt sources, while the Interrupt Priority registers
allow the user to select one of two priority levels for each interrupt. An
interrupt of a high priority may interrupt the service routine of a low
priority interrupt, and if two interrupts of different priority occur
at the same time, the higher level interrupt will be serviced first. An
interrupt cannot be interrupted by another interrupt of the same
priority level. If two interrupts of the same priority level occur simulta-
neously, a polling sequence is observed as shown in Table XXXIII.
Table XXXIII. Priority within an Interrupt Level
Source
Priority
Description
PSMI
WDS
IE0
RDY0/RDY1
TF0
IE1
TF1
I2CI + ISPI
RI + TI
TF2 + EXF2
TII
1 (Highest)
2
3
4
5
6
7
8
9
10
11 (Lowest)
Power Supply Monitor Interrupt
Watchdog Interrupt
External Interrupt 0
ADC Interrupt
Timer/Counter 0 Interrupt
External Interrupt 1
Timer/Counter 1 Interrupt
I
2
C/SPI Interrupt
Serial Interrupt
Timer/Counter 2 Interrupt
Time Interval Counter Interrupt
Interrupt Vectors
When an interrupt occurs the program counter is pushed onto the
stack and the corresponding interrupt vector address is loaded into
the program counter. The interrupt vector addresses are shown
in Table XXXIV.
Table XXXIV. Interrupt Vector Addresses
Source
Vector Address
IE0
TF0
IE1
TF1
RI + TI
TF2 + EXF2
RDY0/RDY1 (ADC)
II
2
C + ISPI
PSMI
TII
WDS (WDIR = 1)
*
0003 Hex
000B Hex
0013 Hex
001B Hex
0023 Hex
002B Hex
0033 Hex
003B Hex
0043 Hex
0053 Hex
005B Hex
*
The watchdog can be configured to generate an interrupt instead of a reset when it
times out. This is used for logging errors or to examine the internal status of the
microcontroller core to understand, from a software debug point of view, why a
watchdog timeout occurred. The watchdog interrupt is slightly different from the
normal interrupts in that its priority level is always set to 1 and it is not possible
to disable the interrupt via the global disable bit (EA) in the IE SFR. This is
done to ensure that the interrupt will always be responded to if a watchdog
timeout occurs. The watchdog will only produce an interrupt if the watchdog
timeout is greater than zero.
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