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參數資料
| 型號： | ADUC824BS |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MicroConverter, Dual-Channel 16-/24-Bit ADCs with Embedded FLASH MCU |
| 中文描述： | 8-BIT, FLASH, 12.58 MHz, MICROCONTROLLER, PQFP52 |
| 封裝： | PLASTIC, MQFP-52 |
| 文件頁數： | 26/68頁 |
| 文件大小： | 1060K |
| 代理商： | ADUC824BS |
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REV. B
ADuC824
–26–
ADCMODE (ADC Mode Register)
Used to control the operational mode of both ADCs.
SFR Address
Power-On Default Value
Bit Addressable
D1H
00H
No
—
—
N
E
0
C
D
A
N
E
1
C
D
A
—
2
D
M
1
D
M
0
D
M
Table IV. ADCMODE SFR Bit Designations
Bit
Name
Description
7
6
5
—
—
ADC0EN
Reserved for Future Use
Reserved for Future Use
Primary ADC Enable
Set
by the user to enable the Primary ADC and place it in the mode selected in MD2–MD0 below
Cleared
by the user to place the Primary ADC in power-down mode.
Auxiliary ADC Enable
Set
by the user to enable the Auxiliary ADC and place it in the mode selected in MD2–MD0 below
Cleared
by the user to place the Auxiliary ADC in power-down mode.
Reserved for Future Use
Primary and Auxiliary ADC Mode bits.
These bits select the operational mode of the enabled ADC as follows:
MD2
MD1
MD0
0
0
0
Power-Down Mode (Power-On Default)
0
0
1
Idle Mode
In Idle Mode the ADC filter and modulator are held in a reset state
although the modulator clocks are still provided.
0
1
0
Single Conversion Mode
In Single Conversion Mode, a single conversion is performed on the
enabled ADC. On completion of the conversion, the ADC data regis-
ters (ADC0H/M/L and/or ADC1H/L) are updated, the relevant flags
in the ADCSTAT SFR are written, and power-down is re-entered with
the MD2–MD0 accordingly being written to 000.
0
1
1
Continuous Conversion
In continuous conversion mode the ADC data registers are regularly
updated at the selected update rate (see SF register)
1
0
0
Internal Zero-Scale Calibration
Internal short is automatically connected to the enabled ADC(s)
1
0
1
Internal Full-Scale Calibration
Internal or External V
REF
(as determined by XREF0 and XREF1 bits
in ADC0/1CON) is automatically connected to the ADC input for
this calibration.
1
1
0
System Zero-Scale Calibration
User should connect system zero-scale input to the ADC input pins
as selected by CH1/CH0 and ACH1/ACH0 bits in the ADC0/1CON
register.
1
1
1
System Full-Scale Calibration
User should connect system full-scale input to the ADC input pins as
selected by CH1/CH0 and ACH1/ACH0 bits in the ADC0/1CON
register.
4
ADC1EN
3
2
1
0
—
MD2
MD1
MD0
NOTES
1. Any change to the MD bits will immediately reset both ADCs. A write to the MD2–0 bits with no change is also treated as a reset. (See exception to this in Note 3 below.)
2. If ADC0CON is written when AD0EN = 1, or if AD0EN is changed from 0 to 1, then both ADCs are also immediately reset. In other words, the Primary ADC is
given priority over the Auxiliary ADC and any change requested on the primary ADC is immediately responded to.
3. On the other hand, if ADC1CON is written or if ADC1EN is changed from 0 to 1, only the Auxiliary ADC is reset. For example, if the Primary ADC is continuously
converting when the Auxiliary ADC change or enable occurs, the primary ADC continues undisturbed. Rather than allow the Auxiliary ADC to operate with a phase
difference from the primary ADC, the Auxiliary ADC will fall into step with the outputs of the primary ADC. The result is that the first conversion time for the
Auxiliary ADC will be delayed up to three outputs while the Auxiliary ADC update rate is synchronized to the Primary ADC.
4. Once ADCMODE has been written with a calibration mode, the RDY0/1 bits (ADCSTAT) are immediately reset and the calibration commences. On completion,
the appropriate calibration registers are written, the relevant bits in ADCSTAT are written, and the MD2–0 bits are reset to 000 to indicate the ADC is back in
power-down mode.
5. Any calibration request of the Auxiliary ADC while the temperature sensor is selected will fail to complete. Although the RDY1 bit will be set at the end of the
calibration cycle, no update of the calibration SFRs will take place and the ERR1 bit will be set.
6. Calibrations are performed at maximum SF (see SF SFR) value guaranteeing optimum calibration operation.
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