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參數資料
| 型號： | ADUC836 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 串行ADC |
| 英文描述： | MicroConverter, Dual 16-Bit-ADCs with Embedded 62 kB Flash MCU |
| 中文描述： | MicroConverter的，雙16位ADC的與嵌入62 kB閃存微控制器 |
| 文件頁數： | 28/80頁 |
| 文件大小： | 5913K |
| 代理商： | ADUC836 |
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ADuC836
–28–
ADC Chopping
Both ADCs on the ADuC836 implement a chopping scheme
whereby the ADC repeatedly reverses its inputs. The decimated
digital output words from the Sinc
3
filters therefore have a positive
offset and negative offset term included.
As a result, a final summing stage is included in each ADC so that
each output word from the filter is summed and averaged with
the previous filter output to produce a new valid output result
to be written to the ADC data SFRs. In this way, while the ADC
throughput or update rate is as discussed earlier and illustrated in
Table VIII, the full settling time through the ADC (or the time to
a first conversion result) will actually be given by 2
t
ADC
.
The chopping scheme incorporated in the ADuC836 ADC results
in excellent dc offset and offset drift specifications and is extremely
beneficial in applications where drift, noise rejection, and optimum
EMI rejection are important factors.
Calibration
The ADuC836 provides four calibration modes that can be pro-
grammed via the mode bits in the ADCMODE SFR detailed in
Table V. In fact, every ADuC836 has already been factory cali-
brated. The resultant Offset and Gain calibration coefficients
for both the primary and auxiliary ADCs are stored on-chip in
manufacturing-specific Flash/EE memory locations. At power-on
or after reset, these factory calibration coefficients are automati-
cally downloaded to the calibration registers in the ADuC836
SFR space. Each ADC (primary and auxiliary) has dedicated
calibration SFRs, which have been described earlier as part of the
general ADC SFR description. However, the factory calibration
values in the ADC calibration SFRs will be overwritten if any
one of the four calibration options are initiated and that ADC is
enabled via the ADC enable bits in ADCMODE.
Even though an internal offset calibration mode is described
below, it should be recognized that both ADCs are chopped. This
chopping scheme inherently minimizes offset and means that an
internal offset calibration should never be required. Also, because
factory 5 V/25°C gain calibration coefficients are automatically
present at power-on an internal full-scale calibration will only be
required if the part is being operated at 3 V or at temperatures
significantly different from 25°C.
The ADuC836 offers internal or system calibration facilities. For
full calibration to occur on the selected ADC, the calibration
logic must record the modulator output for two different input
conditions: zero-scale and full-scale points. These points are
derived by performing a conversion on the different input volt-
ages provided to the input of the modulator during calibration.
The result of the zero-scale calibration conversion is stored in the
Offset Calibration Registers for the appropriate ADC. The result
of the full-scale calibration conversion is stored in the Gain Cali-
bration Registers for the appropriate ADC. With these readings,
the calibration logic can calculate the offset and the gain slope for
the input-to-output transfer function of the converter.
During an internal zero-scale or full-scale calibration, the respective
zero-scale input and full-scale inputs are automatically connected to
the ADC input pins internally to the device. A system calibration,
however, expects the system zero-scale and system full-scale volt-
ages to be applied to the external ADC pins before the calibration
mode is initiated. In this way, external ADC errors are taken into
account and minimized as a result of system calibration. It should
also be noted that to optimize calibration accuracy, all ADuC836
ADC calibrations are carried out automatically at the slowest
update rate.
Internally in the ADuC836, the coefficients are normalized before
being used to scale the words coming out of the digital filter. The
offset calibration coefficient is subtracted from the result prior to
the multiplication by the gain coefficient.
From an operational point of view, a calibration should be treated
like another ADC conversion. A zero-scale calibration (if required)
should always be carried out before a full-scale calibration. System
software should monitor the relevant ADC RDY0/1 bit in the
ADCSTAT SFR to determine end of calibration via a polling
sequence or interrupt driven routine.
REV. A
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相關代理商/技術參數 |
參數描述 |
|---|---|
| ADUC836_02 | 制造商:AD 制造商全稱:Analog Devices 功能描述:MicroConverter, Dual 16-Bit ADCs with Embedded 62 kB Flash MCU |
| ADUC836BCP | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| ADUC836BCPZ | 功能描述:IC MCU 62K FLASH ADC/DAC 56LFCSP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:MicroConverter® ADuC8xx 標準包裝:38 系列:Encore!® XP® 核心處理器:eZ8 芯體尺寸:8-位 速度:5MHz 連通性:IrDA，UART/USART 外圍設備:欠壓檢測/復位，LED，POR，PWM，WDT 輸入/輸出數:16 程序存儲器容量:4KB（4K x 8） 程序存儲器類型:閃存 EEPROM 大小:- RAM 容量:1K x 8 電壓 - 電源 (Vcc/Vdd):2.7 V ~ 3.6 V 數據轉換器:- 振蕩器型:內部 工作溫度:-40°C ~ 105°C 封裝/外殼:20-SOIC（0.295"，7.50mm 寬） 包裝:管件 其它名稱:269-4116Z8F0413SH005EG-ND |
| ADUC836BCPZ-REEL | 功能描述:IC MCU 62K FLASH ADC/DAC 56LFCSP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:MicroConverter® ADuC8xx 標準包裝:38 系列:Encore!® XP® 核心處理器:eZ8 芯體尺寸:8-位 速度:5MHz 連通性:IrDA，UART/USART 外圍設備:欠壓檢測/復位，LED，POR，PWM，WDT 輸入/輸出數:16 程序存儲器容量:4KB（4K x 8） 程序存儲器類型:閃存 EEPROM 大小:- RAM 容量:1K x 8 電壓 - 電源 (Vcc/Vdd):2.7 V ~ 3.6 V 數據轉換器:- 振蕩器型:內部 工作溫度:-40°C ~ 105°C 封裝/外殼:20-SOIC（0.295"，7.50mm 寬） 包裝:管件 其它名稱:269-4116Z8F0413SH005EG-ND |
| ADUC836BS | 制造商:Analog Devices 功能描述:MCU 8-bit ADuC8xx 8052 CISC 62KB Flash 3.3V/5V 52-Pin MQFP 制造商:Analog Devices 功能描述:8BIT MCU +16BIT DUAL ADC MQFP52 |
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