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參數資料
| 型號： | ADUC842BCP62-3 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MicroConverter 12-Bit ADCs and DACs with Embedded High Speed 62-kB Flash MCU |
| 中文描述： | 8-BIT, FLASH, 8.38 MHz, MICROCONTROLLER, QCC56 |
| 封裝： | 8 X 8 MM, LEAD FRAME, MO-220VLLD2, CSP-56 |
| 文件頁數： | 48/88頁 |
| 文件大小： | 903K |
| 代理商： | ADUC842BCP62-3 |
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ADuC841/ADuC842/ADuC843
I
2
C COMPATIBLE INTERFACE
The ADuC841/ADuC842/ADuC843 support a fully licensed
I
2
C serial interface. The I
2
C interface is implemented as a full
hardware slave and software master. SDATA is the data I/O pin,
and SCLOCK is the serial clock. These two pins are shared with
the MOSI and SCLOCK pins of the on-chip SPI interface. To
enable the I
2
C interface, the SPI interface must be turned off
(see SPE in Table 18) or the SPI interface must be moved to
P3.3, P3.4, and P3.5 via the CFG841.1/CFG842.1 bit. Application
Note uC001 describes the operation of this interface as imple-
mented and is available from the MicroConverter website at
. Table 19. I2CCON SFR Bit Designations, Master Mode
Bit No.
Name
Description
7
MDO
I
2
C Software Master Data Output Bit (Master Mode Only).
This data bit is used to implement a master I
2
C transmitter interface in software. Data written to this bit is output on
the SDATA pin if the data output enable (MDE) bit is set.
6
MDE
I
2
C Software Master Data Output Enable Bit (Master Mode Only).
Set by the user to enable the SDATA pin as an output (Tx).
Cleared by the user to enable the SDATA pin as an input (Rx).
5
MCO
I
2
C Software Master Clock Output Bit (Master Mode Only).
This data bit is used to implement a master I
2
C transmitter interface in software. Data written to this bit is output on
the SCLOCK pin.
4
MDI
I
2
C Software Master Data Input Bit (Master Mode Only).
This data bit is used to implement a master I
2
C receiver interface in software. Data on the SDATA pin is latched into
this bit on SCLOCK if the data output enable (MDE) bit is 0.
3
I2CM
I
2
C Master/Slave Mode Bit.
Set by the user to enable I
2
C software master mode.
Cleared by the user to enable I
2
C hardware slave mode.
2
----
Reserved.
1
----
Reserved.
0
----
Reserved.
Rev. 0 | Page 48 of 88
Three SFRs are used to control the I
2
C interface and are
described in the following tables.
I2CCON
SFR Address
Power-On Default
Bit Addressable
I
2
C Control Register
E8H
00H
Yes
Table 20. I2CCON SFR Bit Designations, Slave Mode
Bit No.
Name
Description
7
I2CSI
I
2
C Stop Interrupt Enable Bit.
Set by the user to enable I
2
C stop interrupts. If set, a stop bit that follows a valid start condition generates an
interrupt.
Cleared by the user to disable I
2
C stop interrupts.
6
I2CGC
I
2
C General Call Status Bit.
Set by hardware after receiving a general call address.
Cleared by the user.
5
I2CID1
I
2
C Interrupt Decode Bits.
4
I2CID0
Set by hardware to indicate the source of an I
2
C interrupt.
00 Start and Matching Address.
01 Repeated Start and Matching Address.
10 User Data.
11 Stop after a Start and Matching Address.
3
I2CM
I
2
C Master/Slave Mode Bit.
Set by the user to enable I
2
C software master mode.
Cleared by the user to enable I
2
C hardware slave mode.
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相關代理商/技術參數 |
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|---|---|
| ADUC842BCP62-3U | 制造商:Analog Devices 功能描述:MICROCONVERTER 1-CYCLE VERSION ADUC833 - Trays |
| ADUC842BCP62-3-U2 | 制造商:Analog Devices 功能描述:MICROCONVERTER 1-CYCLE VERSION ADUC834 - Trays |
| ADUC842BCP62-5 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| ADUC842BCP8-3 | 制造商:Analog Devices 功能描述: 制造商:Rochester Electronics LLC 功能描述: |
| ADUC842BCP8-5 | 制造商:Analog Devices 功能描述:MCU 8-Bit ADuC8xx 8052 CISC 62KB Flash 5V 56-Pin LFCSP EP |
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