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參數(shù)資料
型號(hào): ADUC845BCP8-3
廠商: ANALOG DEVICES INC
元件分類: 微控制器/微處理器
英文描述: MicroConverter Multichannel 24-/16-Bit ADCs with Embedded 62 kB Flash and Single-Cycle MCU
中文描述: 8-BIT, FLASH, 12.58 MHz, MICROCONTROLLER, QCC56
封裝: 8 X 8 MM, MO-220-VLLD-2, LFCSP-56
文件頁(yè)數(shù): 25/108頁(yè)
文件大小: 1109K
代理商: ADUC845BCP8-3
ADuC845/ADuC847/ADuC848
Power Control Register (PCON)
The PCON SFR contains bits for power-saving options and
general-purpose status flags as listed in Table 6.
Rev. A | Page 25 of 108
SFR Address:
Power-On Default:
Bit Addressable:
87H
00H
No
Table 6. PCON SFR Bit Designations
Bit No.
Name
7
SMOD
Description
Double UART Baud Rate.
0 = Normal, 1 = Double Baud Rate.
Serial Power-Down Interrupt Enable. If this
bit is set, a serial interrupt from either SPI
or I
2
C can terminate the power-down
mode.
INT0 Power-Down Interrupt Enable.
If this bit is set, either a level (IT0 = 0) or a
negative-going transition (IT0 = 1) on the
INT0 pin terminates power-down mode.
If set to 1, the ALE output is disabled.
General-Purpose Flag Bit.
General-Purpose Flag Bit.
Power-Down Mode Enable. If set to 1, the
part enters power-down mode.
Not Implemented. Write Don’t Care.
6
SERIPD
5
INT0PD
4
3
2
1
ALEOFF
GF1
GF0
PD
0
-----
ADuC845/ADuC847/ADuC848 Configuration Register
(CFG845/CFG847/CFG848)
The CFG845/CFG847/CFG848 SFR contains the bits necessary
to configure the internal XRAM and the extended SP. By default,
it configures the user into 8051 mode, that is, extended SP, and
the internal XRAM are disabled. When using in a program, use
the part name only, that is, CFG845, CFG847, or CFG848.
SFR Address:
Power-On Default:
Bit Addressable:
AFH
00H
No
Table 7. CFG845/CFG847/CFG848 SFR Bit Designations
Bit No.
Name
Description
7
EXSP
Extended SP Enable.
If this bit is set to 1, the stack rolls over
from SPH/SP = 00FFH to 0100H.
If this bit is cleared to 0, SPH SFR is
disabled and the stack rolls over from
SP = FFH to SP = 00H.
6
----
Not Implemented. Write Don’t Care.,
5
----
Not Implemented. Write Don’t Care.
4
----
Not Implemented. Write Don’t Care.
3
----
Not Implemented. Write Don’t Care.
2
----
Not Implemented. Write Don’t Care.
1
----
Not Implemented. Write Don’t Care.
0
XRAMEN
If this bit is set to 1, the internal XRAM is
mapped into the lower 2 kbytes of the
external address space.
If this bit is cleared to 0, the internal XRAM
is accessible and up to 16 MB of external
data memory become available. See
Figure 8.
相關(guān)PDF資料
PDF描述
ADUC847BCP8-3 MicroConverter Multichannel 24-/16-Bit ADCs with Embedded 62 kB Flash and Single-Cycle MCU
ADUC845BCP8-5 MicroConverter Multichannel 24-/16-Bit ADCs with Embedded 62 kB Flash and Single-Cycle MCU
ADUC847BCP8-5 MicroConverter Multichannel 24-/16-Bit ADCs with Embedded 62 kB Flash and Single-Cycle MCU
ADUC845BCP62-3 MicroConverter Multichannel 24-/16-Bit ADCs with Embedded 62 kB Flash and Single-Cycle MCU
ADUC845BCP62-5 MicroConverter Multichannel 24-/16-Bit ADCs with Embedded 62 kB Flash and Single-Cycle MCU
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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