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參數資料
| 型號： | ADV3000 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 3:1 HDMI/DVI Switch with Equalization |
| 中文描述： | 3:1的HDMI / DVI接口與均衡開關 |
| 文件頁數： | 19/28頁 |
| 文件大?。?/td> | 608K |
| 代理商： | ADV3000 |
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ADV3000
PARALLEL INTERFACE CONFIGURATION REGISTERS
The parallel interface configuration registers can be directly set using the PP_EN, PP_CH[1:0], PP_EQ, PP_PRE[1:0], and PP_OCL pins.
This interface is only accessible after the part is reset and before any registers are accessed using the serial control interface. The state of
each pin is set by tying it to 3.3 V (Logic 1) or 0 V (Logic 0).
Rev. 0 | Page 19 of 28
Table 18. Parallel Interface Register Map
Name
Bit 7
High Speed
Device Modes
Bit 6
High speed
switch enable
PP_EN
Auxiliary
switch enable
1
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
High speed source select
0
0
0
0
PP_CH[1]
PP_CH[0]
Auxiliary switch source select
Auxiliary
Device Modes
0
0
0
0
PP_CH[1]
PP_CH[0]
Input termination
on/off select
(termination always on)
1
Receiver
Settings
Source A and Source B input termination pulse-on-source switch select (termination always on)
0
0
0
Input
Termination
Pulse 1
Input
Termination
Pulse 2
Receive
Equalizer 1
0
0
0
0
0
Source C input termination pulse-on-source switch select (termination always on)
0
0
0
0
0
0
0
0
Source A and Source B input equalization level select
PP_EQ
PP_EQ
Source C input equalization level select
PP_EQ
Output pre-emphasis
level select
PP_PE[1]
PP_EQ
PP_EQ
PP_EQ
PP_EQ
PP_EQ
PP_EQ
Receive
Equalizer 2
PP_EQ
PP_EQ
PP_EQ
Output current level
select
PP_OCL
Transmitter
Settings
PP_PE[0]
HIGH SPEED DEVICE MODES REGISTER
PP_EN: High Speed (TMDS) Channels Enable Bit
Table 19. PP_EN Description
PP_EN
Description
0
High speed channels off, low power/standby mode
1
High speed channels on
PP_CH[1:0]: High Speed (TMDS) Switch Source Select Bus
Table 20. High Speed Switch Mode Mapping
PP_CH[1:0]
O[3:0]
00
A[3:0]
01
B[3:0]
10
C[3:0]
11
Description
High Speed Source A switched to output
High Speed Source B switched to output
High Speed Source C switched to output
Illegal Value
AUXILIARY DEVICE MODES REGISTER
The auxiliary (low speed) switch is always enabled when using
the parallel interface.
PP_CH[1:0]: Auxiliary Switch Source Select Bus
Table 21. Auxiliary Switch Mode Mapping
PP_CH[1:0]
AUX_COM[3:0]
00
AUX_A[3:0]
Description
Auxiliary Source A switched
to output
Auxiliary Source B switched
to output
Auxiliary Source C switched
to output
Illegal Value
01
AUX_B[3:0]
10
AUX_C[3:0]
11
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