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參數(shù)資料
| 型號： | ADV7172KST |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 顏色信號轉(zhuǎn)換 |
| 英文描述： | Digital PAL/NTSC Video Encoder with Six DACs 10 Bits, Color Control and Enhanced Power Management |
| 中文描述： | COLOR SIGNAL ENCODER, PQFP48 |
| 封裝： | PLASTIC, TQFP-48 |
| 文件頁數(shù)： | 30/59頁 |
| 文件大?。?/td> | 455K |
| 代理商： | ADV7172KST |
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ADV7172/ADV7173
–30–
REV. A
MR41
MR40
MR47
MR42
MR44
MR43
MR45
MR46
CHROMINANCE
CONTROL
MR44
0
1
ENABLE COLOR
DISABLE COLOR
COLOR BAR
CONTROL
MR46
0
1
DISABLE
ENABLE
VSYNC
3H
MR40
0
1
DISABLE
ENABLE
INTERLACE
CONTROL
0
1
INTERLACED
NONINTERLACED
MR47
BURST
CONTROL
0
1
ENABLE BURST
DISABLE BURST
MR45
CCIR 624/CCIR 601
CONTROL
MR43
0
1
CCIR 624 OUTPUT
CCIR 601 OUTPUT
GENLOCK SELECTION
MR42 MR41
x
0
0
1
DISABLE GENLOCK
ENABLE SUBCARRIER
RESET PIN
ENABLE RTC PIN
1
1
Figure 48. Mode Register 4 (MR4)
MODE REGISTER 4 MR4 (MR47–MR40)
(Address (SR4–SR0) = 04H)
Mode Register 4 is a 8-bit wide register. Figure 48 shows the
various operations under the control of Mode Register 4.
MR4 BIT DESCRIPTION
VSYNC
_3H Control (MR40)
When this bit is enabled (“1”) in slave mode, it is possible to
drive the
VSYNC
active low input for 2.5 lines in PAL mode
and 3 lines in NTSC mode. When this bit is enabled in master
mode, the ADV7172/ADV7173 outputs an active low
VSYNC
signal for 3 lines in NTSC mode and 2.5 lines in PAL mode.
Genlock Control (MR42–MR41)
These bits control the genlock feature of the ADV7172/ADV7173.
Setting MR41 to Logic “0” disables the SCRESET/RTC pin
and allows the ADV7172/ADV7173 to operate in normal mode.
By setting MR41 to “1,” one of two operations may be enabled:
1. If MR42 is set to “0,” the SCRESET/RTC pin is configured
as a subcarrier reset input and the subcarrier phase will reset
to Field 0 whenever a high-to-low field transition is detected
on the SCRESET/RTC pin.
2. If MR42 is set to “1,” the SCRESET/RTC pin is configured
as a real-time control input and the ADV7172/ADV7173 can
be used to lock to an external video source.
Active Video Line Width Control (MR43)
This bit switches between two active video line durations. A
“0” selects ITU-R BT.470 (720 pixels PAL/NTSC) and a “1”
selects ITU-R/SMPTE “analog” standard for active video dura-
tion (710 pixels NTSC, 702 pixels PAL).
Chrominance Control (MR44)
This bit enables the color information to be switched on and off
the video output.
Burst Control (MR45)
This bit enables the color burst information to be switched on
and off the video output.
Color Bar Control (MR46)
This bit can be used to generate and output an internal color
bar test pattern. The color bar configuration is 100/7.5/75/7.5
for NTSC and 100/0/75/0 for PAL. It is important to note that
when color bars are enabled the ADV7172/ADV7173 is config-
ured in a master timing mode. The output pins
VSYNC
/FIELD,
HSYNC
and
BLANK
are three-state during color bar mode.
Interlaced Mode Control (MR47)
This bit is used to setup the output to interlaced or noninter-
laced mode.
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| ADV7172 | Digital PAL/NTSC Video Encoder with Six DACs 10 Bits, Color Control and Enhanced Power Management |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADV7172KST-REEL | 制造商:Analog Devices 功能描述: |
| ADV7172KSTZ | 制造商:Analog Devices 功能描述: |
| ADV7172KSTZ-REEL | 功能描述:IC DAC VIDEO NTSC 6-CH 48-LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編碼器，解碼器，轉(zhuǎn)換器 系列:- 產(chǎn)品變化通告:Development Systems Discontinuation 26/Apr/2011 標(biāo)準(zhǔn)包裝:1 系列:- 類型:編碼器 應(yīng)用:DVB-S.2 系統(tǒng) 電壓 - 電源，模擬:- 電壓 - 電源，數(shù)字:- 安裝類型:- 封裝/外殼:模塊 供應(yīng)商設(shè)備封裝:模塊 包裝:散裝 其它名稱:Q4645799 |
| ADV7173 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Digital PAL/NTSC Video Encoder with Six DACs 10 Bits, Color Control and Enhanced Power Management |
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