- 您現在的位置：買賣IC網 > PDF目錄374046 > ADV7172KST (ANALOG DEVICES INC) Digital PAL/NTSC Video Encoder with Six DACs 10 Bits, Color Control and Enhanced Power Management PDF資料下載
參數資料
| 型號： | ADV7172KST |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 顏色信號轉換 |
| 英文描述： | Digital PAL/NTSC Video Encoder with Six DACs 10 Bits, Color Control and Enhanced Power Management |
| 中文描述： | COLOR SIGNAL ENCODER, PQFP48 |
| 封裝： | PLASTIC, TQFP-48 |
| 文件頁數： | 31/59頁 |
| 文件大小： | 455K |
| 代理商： | ADV7172KST |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁當前第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁
ADV7172/ADV7173
–31–
REV. A
MODE REGISTER 5 MR5 (MR57–MR50)
(Address (SR4-SR0) = 05H)
Mode Register 5 is an 8-bit-wide register. Figure 49 shows the
various operations under the control of Mode Register 5.
MR5 BIT DESCRIPTION
Y-Level Control (MR50)
This bit controls the Y output level on the ADV7172/ADV7173.
If this bit is set (“0”), the encoder outputs SMPTE levels when
configured in PAL mode and Betacam levels when configured in
NTSC mode. If this bit is set (“1”), the encoder outputs Beta-
cam levels when configured in PAL mode and SMPTE levels
when configured in NTSC mode.
UV-Levels Control (MR52–MR51)
These bits control the U and V output levels on the ADV7172/
ADV7173. It is possible to have UV levels with a peak-peak
amplitude of either 700 mV (MR52 + MR51 = “01”) or 1000 mV
(MR52 + MR51 = “10”) in NTSC and PAL. It is also possible
to have default values of 934 mV for NTSC and 700 mV for
PAL (MR52 + MR51 = “00”).
RGB Sync (MR53)
This bit is used to set up the RGB outputs with the sync infor-
mation encoded on all RGB outputs.
Clamp Delay Value (MR55–MR54)
These bits control the delay or advance of the CLAMP signal in
the front or back porch of the ADV7172/ADV7173. It is pos-
sible to delay or advance the pulse by 0, 1, 2 or 3 clock cycles.
Clamp Delay Direction (MR56)
This bit controls a positive or negative delay in the CLAMP
signal. If this bit is set (“1”), the delay is negative. If it is not set
(“0”), the delay is positive.
Clamp Position (MR57)
This bit controls the position of the CLAMP signal. If this bit is
set (“1”), the CLAMP signal is located in the back porch posi-
tion. If this bit is set to (“0”), the CLAMP signal is located in
the front porch position.
MR51
MR50
MR57
MR52
MR54
MR53
MR55
MR56
CLAMP DELAY
DIRECTION
MR56
0
1
POSITIVE
NEGATIVE
CLAMP POSITION
MR57
0
1
FRONT PORCH
BACK PORCH
CLAMP DELAY
MR55 MR54
0
0
1
1
0
1
0
1
NO DELAY
1
3
PCLK
2
3
PCLK
3
3
PCLK
UV LEVEL CONTROL
MR52 MR51
0
0
1
1
0
1
0
1
DEFAULT LEVELS
700 mV
1000 mV
RESERVED
RGB
SYNC
0
1
DISABLE
ENABLE
MR53
Y LEVEL
CONTROL
MR50
0
1
DISABLE
ENABLE
Figure 49. Mode Register 5 (MR5)
相關PDF資料 |
PDF描述 |
|---|---|
| ADV7172 | Digital PAL/NTSC Video Encoder with Six DACs 10 Bits, Color Control and Enhanced Power Management |
| ADV7173 | Digital PAL/NTSC Video Encoder with Six DACs 10 Bits, Color Control and Enhanced Power Management |
| ADV7173* | Digital PAL/NTSC Video Encoder with Six DACs (10 Bits). Color Control and Enhanced Power Management |
| ADV7174 | Chip Scale PAL/NTSC Video Encoder with Advanced Power Management |
| ADV7174BCP | Chip Scale PAL/NTSC Video Encoder with Advanced Power Management |
相關代理商/技術參數 |
參數描述 |
|---|---|
| ADV7172KST-REEL | 制造商:Analog Devices 功能描述: |
| ADV7172KSTZ | 制造商:Analog Devices 功能描述: |
| ADV7172KSTZ-REEL | 功能描述:IC DAC VIDEO NTSC 6-CH 48-LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編碼器，解碼器，轉換器 系列:- 產品變化通告:Development Systems Discontinuation 26/Apr/2011 標準包裝:1 系列:- 類型:編碼器 應用:DVB-S.2 系統 電壓 - 電源，模擬:- 電壓 - 電源，數字:- 安裝類型:- 封裝/外殼:模塊 供應商設備封裝:模塊 包裝:散裝 其它名稱:Q4645799 |
| ADV7173 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Digital PAL/NTSC Video Encoder with Six DACs 10 Bits, Color Control and Enhanced Power Management |
發布緊急采購，3分鐘左右您將得到回復。