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參數資料
| 型號： | ADV7176KS |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 顏色信號轉換 |
| 英文描述： | Integrated Digital CCIR-601 YCrCb to PAL/NTSC Video Encoder |
| 中文描述： | COLOR SIGNAL ENCODER, PQFP44 |
| 封裝： | PLASTIC, QFP-44 |
| 文件頁數： | 15/36頁 |
| 文件大小： | 447K |
| 代理商： | ADV7176KS |
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ADV7175/ADV7176
REV. A
–15–
622
623
624
625
1
2
3
4
5
6
7
21
22
23
DISPLAY
VERTICAL BLANK
ODD FIELD
EVEN FIELD
HSYNC
BLANK
FIELD
DISPLAY
309
310
311
312
313
314
315
316
317
318
319
334
335
336
DISPLAY
VERTICAL BLANK
ODD FIELD
EVEN FIELD
HSYNC
BLANK
FIELD
DISPLAY
320
Figure 25. Timing Mode 3 (PAL)
PAL–Interlaced
: Scan lines 1–6, 311–318 and 624–625 are al-
ways blanked and vertical sync pulses are included in Fields 1,
2, 5 and 6. Scan lines 1–5, 311–319 and 624–625 are always
blanked and vertical sync pulses are included in Fields 3, 4, 7
and 8. T he remaining scan lines in the vertical interval are also
blanked and can be used for close captioning data. Burst is dis-
abled on lines 1–6, 311–318 and 623–625 in Fields 1, 2, 5 and
6. Burst is disabled on lines 1–5, 311–319 and 623–625 in
Fields 3, 4, 7 and 8.
PAL–Noninterlaced
: Scan lines 1–6 and 311–312 are always
blanked and vertical sync pulses are included. T he remaining
scan lines in the vertical interval are also blanked and can be
used for close captioning data. Burst is disabled on lines 1–5,
310–312.
POWE R-ON RE SE T
After power-up, it is necessary to execute a reset operation. A
reset occurs on the falling edge of a high to low transition on the
RESET
pin. T his initializes the pixel port such that the pixel
inputs P7–P0 are selected. After reset, the ADV7175/ADV7176
is automatically set up to operate in NT SC mode. Subcarrier
frequency code 21F07C16 HEX is loaded into the subcarrier
frequency registers. All other registers, with the exception of
Mode Register 0, are set to 00H. All bits in Mode Register 0
are set to Logic Level “0” except Bit MR02. Bit MR02 of
Mode Register 0 is set to Logic “1.” T his enables the 7.5 IRE
pedestal.
In addition the ADV7175/ADV7176 supports a PAL or NT SC
square pixel operation in slave mode. T he part requires an in-
put pixel clock of 24.54 MHz for NT SC and an input pixel
clock of 29.5 MHz for PAL. T he internal horizontal line
counters place the various video waveform sections in the cor-
rect location for the new clock frequencies.
T he ADV7175/ADV7176 has 8 distinct master or slave timing
configurations. T hese are divided into 4 timing modes which
operate at one discrete clock frequency (27 MHz). T iming con-
trol is established with the bidirectional
SYNC
,
BLANK
and
FIELD/
VSYNC
pins. T iming Mode Register 1 can also be
used to vary the timing pulse widths and the where they occur in
relation to each other.
OUT PUT VIDE O T IMING
T he video timing generator generates the appropriate SYNC,
BLANK and BURST sequence that controls the output analog
waveforms. T hese sequences are summarized below. In slave
modes the following sequences are synchronized with the input
timing control signals. In master modes the timing generator
free runs and generates the following sequences in addition to
the output timing control signals.
NT SC–Interlaced
: Scan lines 1–9 and 264–272 are always
blanked and vertical sync pulses are included. Scan lines 525,
10–21 and 262, 263, 273–284 are also blanked and can be used
for close captioning data. Burst is disabled on lines 1–6, 261–
269 and 523–525.
NT SC–Noninterlaced
: Scan lines 1–9 are always blanked
and vertical sync pulses are included. Scan lines 10–21 are also
blanked and can be used for close captioning data. Burst is dis-
abled on lines 1–6, 261–262.
(Continued from page 8)
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