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參數(shù)資料
| 型號： | ADV7176KS |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 顏色信號轉換 |
| 英文描述： | Integrated Digital CCIR-601 YCrCb to PAL/NTSC Video Encoder |
| 中文描述： | COLOR SIGNAL ENCODER, PQFP44 |
| 封裝： | PLASTIC, QFP-44 |
| 文件頁數(shù)： | 17/36頁 |
| 文件大?。?/td> | 447K |
| 代理商： | ADV7176KS |
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ADV7175/ADV7176
REV. A
–17–
SR4
SR3
SR2
SR1
SR0
SR7
SR6
SR5
SR4
SR3 SR2 SR1 SR0
ZERO SHOULD
BE WRITTEN TO
THESE BITS
SR7–SR5
(000)
SUBADDRESS REGISTER
0 0 0 0 0 MODE REGISTER 0
0 0 0 0 1 MODE REGISTER 1
0 0 0 1 0 SUB CARRIER FREQ REGISTER 0
0 0 0 1 1 SUB CARRIER FREQ REGISTER 1
0 0 1 0 0 SUB CARRIER FREQ REGISTER 2
0 0 1 0 1 SUB CARRIER FREQ REGISTER 3
0 0 1 1 0 SUB CARRIER PHASE REGISTER
0 0 1 1 1 TIMING MODE REGISTER 0
0 1 0 0 0 CLOSED CAPTIONING EXTENDED DATA – BYTE 0
0 1 0 0 1 CLOSED CAPTIONING EXTENDED DATA – BYTE 1
0 1 0 1 0 CLOSED CAPTIONING DATA – BYTE 0
0 1 0 1 1 CLOSED CAPTIONING DATA – BYTE 1
0 1 1 0 0 TIMING MODE REGISTER 1
0 1 1 0 1 MODE REGISTER 2
0 1 1 1 0 NTSC PEDESTAL CONTROL REG 0 (FIELD 1/3)
0 1 1 1 1 NTSC PEDESTAL CONTROL REG 1 (FIELD 1/3)
1 0 0 0 0 NTSC PEDESTAL CONTROL REG 2 (FIELD 2/4)
1 0 0 0 1 NTSC PEDESTAL CONTROL REG 3 (FIELD 2/4)
1 0 0 1 0 MODE REGISTER 3
1 0 0 1 1 MACROVISION REGISTERS (ADV7175 ONLY)
"
"
1 1 1 1 1 MACROVISION REGISTERS (ADV7175 ONLY)
"
"
"
"
Figure 30. Subaddress Register
RE GIST E R ACCE SSE S
T he MPU can write to or read from all of the registers of the
ADV7175/ADV7176 except the subaddress register which is a
write only register. T he subaddress register determines which
register the next read or write operation accesses. All communi-
cations with the part through the bus start with an access to the
subaddress register. T hen a read/write operation is performed
from/to the target address which then increments to the next
address until a stop command on the bus is performed.
RE GIST E R PROGRAMMING
T he following section describes each register, including
subaddress register, mode registers, subcarrier frequency regis-
ters, subcarrier phase register, timing registers, closed captioning
extended data registers, closed captioning data registers and
NT SC pedestal control registers in terms of its configuration.
Subaddress Register (SR7–SR0)
T he communications register is an eight bit write-only register.
After the part has been accessed over the bus and a read/write
operation is selected, the subaddress set up. T he subaddress
register determines to/from which register the operation takes
place.
Figure 30 shows the various operations under the control of the
subaddress register. Zero should always be written to SR7–
SR5.
Register Select (SR4–SR0):
T hese bits are setup to point to the required starting address.
MODE RE GIST E R 0 MR0 (MR07–MR00)
(Address (SR4–SR0) = 00H)
Mode Register 0 is a 8-bit wide register.
Figure 31 shows the various operations under the control of
Mode Register 0. T his register can be read from as well written to.
MR01
MR00
MR07
MR02
MR04
MR03
MR05
MR06
OUTPUT VIDEO
STANDARD SELECTION
0
0
1
1
0
1
0
1
NTSC
PAL (B, D, G, H, I)
PAL (M)
RESERVED
MR01 MR00
MR07
(0)
ZERO SHOULD
BE WRITTEN TO
THIS BIT
OUTPUT SELECT
MR06
0
1
YC OUTPUT
RGB/YUV OUTPUT
FILTER SELECT
0
0
1
1
0
1
0
1
LOW PASS FILTER (A)
NOTCH FILTER
EXTENDED MODE
LOW PASS FILTER (B)
MR04 MR03
RGB SYNC
MR05
0
1
DISABLE
ENABLE
PEDESTAL CONTROL
MR02
0
1
PEDESTAL OFF
PEDESTAL ON
Figure 31. Mode Register 0
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| ADV7177KSZ | 功能描述:IC DAC VIDEO NTSC 3-CH 44MQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編碼器，解碼器，轉換器 系列:- 產(chǎn)品變化通告:Development Systems Discontinuation 26/Apr/2011 標準包裝:1 系列:- 類型:編碼器 應用:DVB-S.2 系統(tǒng) 電壓 - 電源，模擬:- 電壓 - 電源，數(shù)字:- 安裝類型:- 封裝/外殼:模塊 供應商設備封裝:模塊 包裝:散裝 其它名稱:Q4645799 |
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