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參數資料
| 型號： | ADV7176KS |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 顏色信號轉換 |
| 英文描述： | Integrated Digital CCIR-601 YCrCb to PAL/NTSC Video Encoder |
| 中文描述： | COLOR SIGNAL ENCODER, PQFP44 |
| 封裝： | PLASTIC, QFP-44 |
| 文件頁數： | 19/36頁 |
| 文件大小： | 447K |
| 代理商： | ADV7176KS |
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ADV7175/ADV7176
REV. A
–19–
SUBCARRIE R FRE QUE NCY RE GIST E RS 3–0 (FSC3–FSC0)
(Address (SR4–SR0) = 05H–02H)
T hese 8-bit wide registers are used to set up the subcarrier fre-
quency. T he value of these registers are calculated by using the
following equation:
Subcarrier Frequency Register
=
2
32
±1
F
CLK
*
F
SCF
i.e.: NT SC Mode,
F
CLK
= 27 MHz, F
SCF
= 3.5796 MHz
S
ubcarrier Frequency Register
=
Subcarrier Frequency Register
= 21F07C16
HEX
Figure 33 shows how the frequency is set up by the 4 registers.
2
32
±1
27
×
10
6
*3.579545
×
10
6
SUBCARRIER
FREQUENCY
REG 0
SUBCARRIER
FREQUENCY
REG 1
SUBCARRIER
FREQUENCY
REG 2
SUBCARRIER
FREQUENCY
REG 3
FSC6
FSC5
FSC3
FSC1
FSC4
FSC2
FSC0
FSC7
FSC30 FSC29
FSC27
FSC25
FSC28
FSC26
FSC24
FSC31
FSC22 FSC21
FSC19
FSC17
FSC20
FSC18
FSC16
FSC23
FSC14 FSC13
FSC11
FSC9
FSC12
FSC10
FSC8
FSC15
Figure 33. Subcarrier Frequency Register
SUBCARRIE R PHASE RE GIST E R (FP7–FP0):
(Address (SR4–SR0) = 06H)
T his 8-bit wide register is used to set up the subcarrier phase.
Each bit represents 1.41
°
.
T IMING RE GIST E R 0 (T R07–T R00)
(Address (SR4-SR0) = 07H)
T iming Register 0 is a 8-bit wide register.
Figure 34 shows the various operations under the control of
T iming Register 0. T his register can be read from as well
written to.
T IMING RE GIST E R 0 (T R07–T R00)
BIT DE SCRIPT ION
Master/Slave Control (T R00)
T his bit controls whether the ADV7175/ADV7176 is in master
or slave mode.
T iming Mode Control (T R02–T R01)
T hese bits control the timing mode of the ADV7175/ADV7176
T hese modes are described in the T iming and Control section
of the data sheet.
BLANK
Control (T R03)
T his bit controls whether the
BLANK
input is used when the
part is in slave mode.
Luma Delay Control (T R05–T R04)
T hese bits control the addition of a luminance delay. Each bit
represents a delay of 74 ns.
Pixel Port Select (T R06)
T his bit is used to set the pixel port to accept 8-bit or 16-bit
data. If an 8-bit input is selected the data will be set up on
Pins P7–P0.
T iming Register Reset (T R07)
T oggling T R07 from low to high and low again resets the inter-
nal timing counters. T his bit should be toggled after setting up a
new timing mode.
TR01
TR00
TR07
TR02
TR03
TR05
TR06
TR04
TIMING
REGISTER RESET
TR07
BLACK INPUT
CONTROL
TR03
0
1
ENABLE
DISABLE
PIXEL PORT
CONTROL
TR06
0
1
8-BIT
16-BIT
MASTER/SLAVE
CONTROL
TR00
0
1
SLAVE TIMING
MASTER TIMING
LUMA DELAY
0
0
1
1
0
1
0
1
0ns DELAY
74ns DELAY
148ns DELAY
222ns DELAY
TR05 TR04
TIMING MODE
SELECTION
0
0
1
1
0
1
0
1
MODE 0
MODE 1
MODE 2
MODE 3
TR02 TR01
Figure 34. Timing Register 0
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| ADV7177KSZ | 功能描述:IC DAC VIDEO NTSC 3-CH 44MQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編碼器，解碼器，轉換器 系列:- 產品變化通告:Development Systems Discontinuation 26/Apr/2011 標準包裝:1 系列:- 類型:編碼器 應用:DVB-S.2 系統 電壓 - 電源，模擬:- 電壓 - 電源，數字:- 安裝類型:- 封裝/外殼:模塊 供應商設備封裝:模塊 包裝:散裝 其它名稱:Q4645799 |
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