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參數資料
| 型號： | ADV7178KS |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 顏色信號轉換 |
| 英文描述： | Integrated Digital CCIR-601 to PAL/NTSC Video Encoder |
| 中文描述： | COLOR SIGNAL ENCODER, PQFP44 |
| 封裝： | PLASTIC, MO-112-AA-1, MQFP-44 |
| 文件頁數： | 25/38頁 |
| 文件大小： | 280K |
| 代理商： | ADV7178KS |
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ADV7177/ADV7178
–25–
REV. 0
TR01
TR00
TR07
TR02
TR03
TR05
TR06
TR04
TIMING
REGISTER RESET
TR07
BLACK INPUT
CONTROL
TR03
0
1
ENABLE
DISABLE
PIXEL PORT
CONTROL
TR06
0
1
8-BIT
16-BIT
MASTER/SLAVE
CONTROL
TR00
0
1
SLAVE TIMING
MASTER TIMING
LUMA DELAY
0
0
1
1
0
1
0
1
0ns DELAY
74ns DELAY
148ns DELAY
222ns DELAY
TR05 TR04
TIMING MODE
SELECTION
TR02 TR01
0
0
1
1
0
1
0
1
MODE 0
MODE 1
MODE 2
MODE 3
Figure 35. Timing Register 0
TR11
TR10
TR17
TR12
TR13
TR15
TR16
TR14
HSYNC
WIDTH
0
0
1
1
0
1
0
1
1 x T
PCLK
4 x T
PCLK
16 x T
PCLK
128 x T
PCLK
TR11 TR10
T
A
HSYNC
TO FIELD
RISING EDGE DELAY
(MODE 1 ONLY)
x
x
0
1
T
B
T
B
+ 32
m
s
TR15 TR14
T
C
HSYNC
TO PIXEL
DATA ADJUSTMENT
TR17 TR16
0
0
1
1
0
1
0
1
0 x T
PCLK
1 x T
PCLK
2 x T
PCLK
3 x T
PCLK
HSYNC
TO
FIELD/
VSYNC
DELAY
TR13 TR12
0
0
1
1
0
1
0
1
0 x T
PCLK
4 x T
PCLK
8 x T
PCLK
16 x T
PCLK
VSYNC
WIDTH
(MODE 2 ONLY)
TR15 TR14
0
0
1
1
0
1
0
1
1 x T
PCLK
4 x T
PCLK
16 x T
PCLK
128 x T
PCLK
LINE 313
LINE 314
LINE 1
T
B
TIMING MODE 1 (MASTER/PAL)
HSYNC
FIELD/
VSYNC
T
A
T
C
T
B
Figure 38. Timing Register 1
Luma Delay Control (TR05–TR04)
These bits control the addition of a luminance delay. Each bit
represents a delay of 74 ns.
Pixel Port Select (TR06)
This bit is used to set the pixel port to accept 8-bit or 16-bit data.
If an 8-bit input is selected the data will be set up on Pins P7–P0.
Timing Register Reset (TR07)
Toggling TR07 from low to high and low again resets the inter-
nal timing counters. This bit should be toggled after power-up,
reset or changing to a new timing mode.
CLOSED CAPTIONING EVEN FIELD
DATA REGISTER 1–0 (CED15–CED00)
(Address [SR4–SR0] = 09–08H)
These 8-bit-wide registers are used to set up the closed captioning
extended data bytes on even fields. Figure 36 shows how the
high and low bytes are set up in the registers.
BYTE 1
BYTE 0
CED6
CED5
CED3
CED1
CED4
CED2
CED0
CED7
CED14
CED13
CED11
CED9
CED12
CED10
CED8
CED15
Figure 36. Closed Captioning Extended Data Register
CLOSED CAPTIONING ODD FIELD
DATA REGISTER 1–0 (CCD15–CCD00)
(Subaddress [SR4–SR0] = 0B–0AH)
These 8-bit-wide registers are used to set up the closed captioning
data bytes on odd fields. Figure 37 shows how the high and low
bytes are set up in the registers.
BYTE 1
BYTE 0
CCD6
CCD5
CCD3
CCD1
CCD4
CCD2
CCD0
CCD7
CCD14
CCD13
CCD11
CCD9
CCD12
CCD10
CCD8
CCD15
Figure 37. Closed Captioning Data Register
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相關代理商/技術參數 |
參數描述 |
|---|---|
| ADV7178KS-REEL | 制造商:Analog Devices 功能描述: |
| ADV7179 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Chip Scale PAL/NTSC Video Encoder with Advanced Power Management |
| ADV7179BCP | 制造商:Analog Devices 功能描述:Video Encoder 3DAC 10-Bit 40-Pin LFCSP EP 制造商:Analog Devices 功能描述:IC VIDEO ENCODER |
| ADV7179BCP1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Chip Scale PAL/NTSC Video Encoder with Advanced Power Management |
| ADV7179BCP-REEL | 制造商:Analog Devices 功能描述:Video Encoder 3DAC 10-Bit 40-Pin LFCSP EP T/R |
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