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參數資料
| 型號： | ADV7202 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | Codec |
| 英文描述： | Simultaneous Sampling Video Rate Codec |
| 中文描述： | 同時采樣率視頻編解碼器 |
| 文件頁數： | 12/26頁 |
| 文件大小： | 216K |
| 代理商： | ADV7202 |
REV. PrB
PRELIMINARY TECHNICAL DATA
ADV7202
–12–
XTAL0
DAC_DATA [9:0]
SYNC_OUT
CR
Y
CB
Y
CR
Y
CB
Figure 3. SYNC_OUT Output Timing, YCrCb Input
MPU PORT DESCRIPTION
The ADV7202 supports a 2-wire serial (I
2
C-compatible)
microprocessor bus driving multiple peripherals. Two inputs,
Serial Data (SDA) and Serial Clock (SCL), carry information
between any device connected to the bus. Each slave device is
recognized by a unique address. The ADV7202 has four pos-
sible slave addresses for both read and write operations. These
are unique addresses for each device and are illustrated in
Figure 4. The LSB sets either a read or write operation. Logic
Level “1” corresponds to a read operation, while Logic Level
“0” corresponds to a write operation. A1 is set by setting the
ALSB pin of the ADV7202 to Logic Level “0” or Logic Level
“1.” When ALSB is set to “0,” there is greater input bandwidth
on the I
2
C lines, which allows high-speed data transfers on this
bus. When ALSB is set to “1,” there is reduced input band-
width on the I
2
C lines, which means that pulses of less than
50 ns will not pass into the I
2
C internal controller. This mode is
recommended for noisy systems.
0
0
1
0
1
1
A1
X
0
1
DISABLED
ENABLED
READ/WRITE
CONTROL
SET UP BY
ALSB
ADDRESS
CONTROL
Figure 4. Slave Address
To control the various devices on the bus, the following proto-
col must be followed. First the master initiates a data transfer by
establishing a Start condition, defined by a high-to-low transition
on SDA while SCL remains high. This indicates that an address/
data stream will follow. All peripherals respond to the Start
condition and shift the next eight bits (7-bit address + R/
W
bit).
The bits are tranferred from MSB down to LSB. The peripheral
that recognizes the transmitted address responds by pulling the
data line low during the ninth clock pulse. This is known as an
Acknowledge Bit. All other devices withdraw from the bus at
this point and maintain an idle condition. The idle condition
is where the device monitors the SDA and SCL lines waiting for
the Start condition and the correct transmitted address. The R/
W
bit determines the direction of the data.
A Logic “0” on the LSB of the first byte means that the master
will write information to the peripheral. A Logic “1” on the LSB
of the first byte means that the master will read information
from the peripheral.
The ADV7202A acts as a standard slave device on the bus. The
data on the SDA pin is eight bits long, supporting the 7-bit
addresses plus the R/
W
bit. It interprets the first byte as the
device address and the second byte as the starting subaddress.
The subaddresses auto-increment, allowing data to be written to
or read from the starting subaddress. A data transfer is always
terminated by a Stop condition. The user can access any unique
subaddress register on a one-by-one basis without updating all
the registers.
Stop and Start conditions can be detected at any stage during
the data transfer. If these conditions are asserted out of sequence
with normal read and write operations, they cause an immediate
jump to the idle condition. During a given SCL high period, the
user should only issue one Start condition, one Stop condition,
or a single Stop condition followed by a single Start condition. If
an invalid subaddress is issued by the user, the ADV7202 will
not issue an acknowledge and will return to the idle condition. If
in auto-increment mode, the user exceeds the highest subaddress,
the following action will be taken:
1. In Read Mode, the highest subaddress register contents
will continue to be output until the master device issues a
no-acknowledge. This indicates the end of a read. A
no-acknowledge condition is where the SDA line is not
pulled low on the ninth pulse.
2. In Write Mode, the data for the invalid byte will not be
loaded into any subaddress register, a no-acknowledge will
be issued by the ADV7202, and the part will return to the
idle condition.
Figure 5 illustrates an example of data transfer for a read
sequence and the Start and Stop conditions.
1–7
8
9
1–7
8
9
1–7
8
9
P
S
START ADDR R/
W
ACK SUBADDRESS ACK
DATA
ACK
STOP
SDATA
SCLOCK
Figure 5. Bus Data Transfer
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相關代理商/技術參數 |
參數描述 |
|---|---|
| ADV7202KST | 制造商:Rochester Electronics LLC 功能描述:27MHZ DTV PICTURE IN PICTURE CODEC I.C. - Bulk 制造商:Analog Devices 功能描述: |
| ADV7202KSTZ | 功能描述:IC CODEC VIDEO 10BIT 64LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編解碼器 系列:- 標準包裝:2,500 系列:- 類型:立體聲音頻 數據接口:串行 分辨率（位）:18 b ADC / DAC 數量:2 / 2 三角積分調變:是 S/N 比，標準 ADC / DAC (db):81.5 / 88 動態范圍，標準 ADC / DAC (db):82 / 87.5 電壓 - 電源，模擬:2.6 V ~ 3.3 V 電壓 - 電源，數字:1.7 V ~ 3.3 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-WFQFN 裸露焊盤 供應商設備封裝:48-TQFN-EP（7x7） 包裝:帶卷 (TR) |
| ADV7280ABCPZ-M | 功能描述:10-BIT SD VIDEO DECODER 制造商:analog devices inc. 系列:- 包裝:托盤 零件狀態:在售 類型:視頻 數據接口:I2C，串行 分辨率（位）:10 b ADC/DAC 數:1 / 0 三角積分:無 信噪比，ADC/DAC（db）（典型值）:- 動態范圍，ADC/DAC（db）（典型值）:- 電壓 - 電源，模擬:1.71 V ~ 1.89 V 電壓 - 電源，數字:1.71 V ~ 1.89 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:32-WFQFN 裸露焊盤，CSP 供應商器件封裝:32-LFCSP-WQ（5x5） 標準包裝:1 |
| ADV7280ABCPZ-M-RL | 功能描述:10-BIT SD VIDEO DECODER 制造商:analog devices inc. 系列:* 零件狀態:在售 標準包裝:5,000 |
| ADV7280AWBCPZ | 功能描述:10-BIT SD VIDEO DECODER 制造商:analog devices inc. 系列:- 包裝:托盤 零件狀態:在售 類型:視頻 數據接口:I2C 分辨率（位）:10 b ADC/DAC 數:1 / 0 三角積分:無 信噪比，ADC/DAC（db）（典型值）:- 動態范圍，ADC/DAC（db）（典型值）:- 電壓 - 電源，模擬:1.71 V ~ 1.89 V 電壓 - 電源，數字:1.71 V ~ 1.89 V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:32-WFQFN 裸露焊盤，CSP 供應商器件封裝:32-LFCSP-WQ（5x5） 標準包裝:1 |
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