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參數資料
| 型號： | ADV7202 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | Codec |
| 英文描述： | Simultaneous Sampling Video Rate Codec |
| 中文描述： | 同時采樣率視頻編解碼器 |
| 文件頁數： | 25/26頁 |
| 文件大?。?/td> | 216K |
| 代理商： | ADV7202 |
REV. PrB
PRELIMINARY TECHNICAL DATA
ADV7202
–25–
CLAMP CONTROL
The clamp control has 2 modes of operation, if the Synchronize
clamp control bit CR16 (bit-6 address 07h) is set to on the
clamps that are enabled will be switched on for the programmed
time when triggered by the Sync_in control signal, this control
signal is edge detected and its polarity can be set by MR35 (bit-5
address 03h). If the Synchronize clamp control bit is set to zero,
when enabled each clamp will switch on for the programmed time,
the enabled signal is edge detected hence the bit must first be
reset to zero before the next enable signal can be implemented.
DAC TERMINATION AND LAYOUT CONSIDERATIONS
The ADV7202 contains an on-board voltage reference. The
VREF pin is normally terminated to AVDD through a 0.1
μ
F
capacitor when the internal VREF is used. Alternatively, the
ADV7202 can be used with an external VREF (AD589).
Resistor RSET is connected between the RSET pin and AVSS
and is used to control the amplitude of the DAC output current.
I
MAX
= 5.196/Rset Amps
Therefore, a recommended RSET value of 1200
will enable
an I
MAX
of 4.43 mA. V
MAX
= Rload
×
I
MAX
, Rload should have a
value of 300
.
The ADV7202 has four analog outputs—DAC0, DAC1, DAC2,
and DAC3. The DACs must be used with external buffer circuits
in order to provide sufficient current to drive an output device.
Suitable op amps are the AD8009, AD8002, AD8001, or AD8057.
PC BOARD LAYOUT CONSIDERATIONS
The ADV7202 is optimally designed for lowest noise performance,
both radiated and conducted noise. To complement the excel-
lent noise performance of the ADV7202, it is imperative that
great care be given to the PC board layout.
The layout should be optimized for lowest noise on the ADV7202
power and ground lines. This can be achieved by shielding the
digital inputs and providing good decoupling. The lead length
between groups of AVDD, AVSS, DVDD, and DVSS pins
should be kept as short as possible to minimize inductive ringing.
It is recommended that a 4-layer printed circuit board be
used, with power and ground planes separating the layer of the
signal carrying traces of the components and solder side layer.
Placement of components should be considered to separate
noisy circuits such as crystal clocks, high-speed logic circuitry,
and analog circuitry.
There should be a separate analog ground plane (AVSS) and a
separate digital ground plane (DVSS).
Power planes should encompass a digital power plane (DVDD)
and an analog power plane (AVDD). The analog power plane
should contain the DACs and all associated circuitry, VREF
circuitry. The digital power plane should contain all logic
circuitry. The analog and digital power planes should be individually
connected to the common power plane at one single point through
a suitable filtering device such as a ferrite bead.
DAC output traces on a PCB should be treated as transmission
lines. It is recommended that the DACs be placed as close as
possible to the output connector, with the analog output traces
being as short as possible (less than three inches). The DAC
termination resistors should be placed as close as possible to
the DAC outputs and should overlay the PCB’s ground plane.
As well as minimizing reflections, short analog output traces will
reduce noise pickup due to neighboring digital circuitry.
Supply Decoupling
Noise on the analog power plane can be further reduced by the
use of decoupling capacitors.
Optimum performance is achieved by the use of 0.1
μ
F ceramic
capacitors. Each of the group of AVDD or DVDD pins should
be individually decoupled to ground. This should be done by
placing the capacitors as close as possible to the device with the
capacitor leads as short as possible, thus minimizing lead
inductance.
Digital Signal Interconnect
The digital signal lines should be isolated as much as possible
from the analog outputs and other analog circuitry. Digital
signal lines should not overlay the analog power plane.
Due to the high clock rates used, long clock lines to the ADV7202
should be avoided to minimize noise pickup.
Any active pull-up termination resistors for the digital inputs
should be connected to the digital power plane and not the
analog power plane.
Analog Signal Interconnect
The ADV7202 should be located as close as possible to the output
connectors, thus minimizing noise pickup and reflections due to
impedance mismatch.
For optimum performance, the analog outputs should each be
source and load terminated, as shown in Figure TBD. The
termination resistors should be as close as possible to the
ADV7202 to minimize reflections.
Any unused inputs should be tied to the ground.
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相關代理商/技術參數 |
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|---|---|
| ADV7202KST | 制造商:Rochester Electronics LLC 功能描述:27MHZ DTV PICTURE IN PICTURE CODEC I.C. - Bulk 制造商:Analog Devices 功能描述: |
| ADV7202KSTZ | 功能描述:IC CODEC VIDEO 10BIT 64LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編解碼器 系列:- 標準包裝:2,500 系列:- 類型:立體聲音頻 數據接口:串行 分辨率（位）:18 b ADC / DAC 數量:2 / 2 三角積分調變:是 S/N 比，標準 ADC / DAC (db):81.5 / 88 動態范圍，標準 ADC / DAC (db):82 / 87.5 電壓 - 電源，模擬:2.6 V ~ 3.3 V 電壓 - 電源，數字:1.7 V ~ 3.3 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-WFQFN 裸露焊盤 供應商設備封裝:48-TQFN-EP（7x7） 包裝:帶卷 (TR) |
| ADV7280ABCPZ-M | 功能描述:10-BIT SD VIDEO DECODER 制造商:analog devices inc. 系列:- 包裝:托盤 零件狀態:在售 類型:視頻 數據接口:I2C，串行 分辨率（位）:10 b ADC/DAC 數:1 / 0 三角積分:無 信噪比，ADC/DAC（db）（典型值）:- 動態范圍，ADC/DAC（db）（典型值）:- 電壓 - 電源，模擬:1.71 V ~ 1.89 V 電壓 - 電源，數字:1.71 V ~ 1.89 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:32-WFQFN 裸露焊盤，CSP 供應商器件封裝:32-LFCSP-WQ（5x5） 標準包裝:1 |
| ADV7280ABCPZ-M-RL | 功能描述:10-BIT SD VIDEO DECODER 制造商:analog devices inc. 系列:* 零件狀態:在售 標準包裝:5,000 |
| ADV7280AWBCPZ | 功能描述:10-BIT SD VIDEO DECODER 制造商:analog devices inc. 系列:- 包裝:托盤 零件狀態:在售 類型:視頻 數據接口:I2C 分辨率（位）:10 b ADC/DAC 數:1 / 0 三角積分:無 信噪比，ADC/DAC（db）（典型值）:- 動態范圍，ADC/DAC（db）（典型值）:- 電壓 - 電源，模擬:1.71 V ~ 1.89 V 電壓 - 電源，數字:1.71 V ~ 1.89 V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:32-WFQFN 裸露焊盤，CSP 供應商器件封裝:32-LFCSP-WQ（5x5） 標準包裝:1 |
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