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參數(shù)資料
| 型號： | ADV7341BSTZ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | Multiformat Video Encoder, Six 12-Bit Noise Shaped Video㈢ DACS |
| 中文描述： | SERIAL INPUT LOADING, 12-BIT DAC, PQFP64 |
| 封裝： | ROHS COMPLIANT, MS-026BCD, LQFP-64 |
| 文件頁數(shù)： | 29/88頁 |
| 文件大?。?/td> | 1066K |
| 代理商： | ADV7341BSTZ |
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ADV7340/ADV7341
Rev. 0 | Page 29 of 88
Table 15. Register 0x01 to Register 0x09
SR7 to
SR0
Register
0x01
Mode Select
Register
Bit Description
Reserved.
DDR Clock Edge Alignment.
Note: Only used for ED
1
and
HD DDR modes.
Bit Number
5
4
Register Setting
Chroma clocked in on rising clock edge;
luma clocked in on falling clock edge.
Reserved.
Reserved.
Luma clocked in on rising clock edge;
chroma clocked in on falling clock edge.
SD input only.
ED/HD-SDR input only.
ED/HD-DDR input only.
SD and ED/HD-SDR.
SD and ED/HD-DDR.
Reserved.
Reserved.
ED only (at 54 MHz).
Allows data to be applied to data ports in
various configurations (SD feature only).
Reset
Value
0x00
7
6
3
2
0
1
0
0
0
0
1
1
1
0
1
Reserved.
Input Mode.
Note: See Reg. 0x30, Bits[7:3]
for ED/HD format selection.
0
1
0
0
0
0
1
1
1
1
0
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
0
1
0
0
Y/C/S Bus Swap.
Reserved.
Test Pattern Black Bar.
2
0 must be written to these bits.
Disabled.
Enabled.
Disable manual CSC matrix adjust.
Enable manual CSC matrix adjust.
No sync.
Sync on all RGB outputs.
RGB component outputs.
YPrPb component outputs.
No sync output.
Output SD syncs on S_HSYNC and
S_VSYNC pins.
No sync output.
Output ED/HD syncs on S_HSYNC and
S_VSYNC pins.
LSBs for GY.
0x20
Manual CSC Matrix Adjust.
Sync on RGB.
RGB/YPrPb Output Select.
SD Sync Output Enable.
0
1
0x02
Mode
Register 0
ED/HD Sync Output Enable.
0x03
ED/HD CSC
Matrix 0
ED/HD CSC
Matrix 1
x
x
0x03
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
LSBs for RV.
LSBs for BU.
LSBs for GV.
LSBs for GU.
Bits[9:2 ] for GY.
0xF0
0x04
0x05
ED/HD CSC
Matrix 2
ED/HD CSC
Matrix 3
ED/HD CSC
Matrix 4
ED/HD CSC
Matrix 5
ED/HD CSC
Matrix 6
0x4E
0x06
x
x
x
x
x
x
x
x
Bits[9:2] for GU.
0x0E
0x07
x
x
x
x
x
x
x
x
Bits[9:2] for GV.
0x24
0x08
x
x
x
x
x
x
x
x
Bits[9:2] for BU.
0x92
0x09
x
x
x
x
x
x
x
x
Bits[9:2] for RV.
0x7C
1
ED = enhanced definition = 525p and 625p.
2
Subaddress 0x31, Bit 2 must also be enabled (ED/HD). Subaddress 0x84, Bit 6 must also be enabled (SD).
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADV7341EBZ | 制造商:AD 制造商全稱:Analog Devices 功能描述:Multiformat Video Encoder, Six 12-Bit Noise Shaped Video㈢ DACS |
| ADV7342 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Multiformat Video Encoder Six, 11-Bit, 297 MHz DACs |
| ADV7342BSTZ | 制造商:AD 制造商全稱:Analog Devices 功能描述:Multiformat Video Encoder Six, 11-Bit, 297 MHz DACs |
| ADV7343 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Multiformat Video Encoder Six, 11-Bit, 297 MHz DACs |
| ADV7343BSTZ | 功能描述:IC ENCODER VIDEO W/DAC 64-LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編碼器，解碼器，轉(zhuǎn)換器 系列:- 產(chǎn)品變化通告:Development Systems Discontinuation 26/Apr/2011 標準包裝:1 系列:- 類型:編碼器 應(yīng)用:DVB-S.2 系統(tǒng) 電壓 - 電源，模擬:- 電壓 - 電源，數(shù)字:- 安裝類型:- 封裝/外殼:模塊 供應(yīng)商設(shè)備封裝:模塊 包裝:散裝 其它名稱:Q4645799 |
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