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參數資料
| 型號： | ADV7341BSTZ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | Multiformat Video Encoder, Six 12-Bit Noise Shaped Video㈢ DACS |
| 中文描述： | SERIAL INPUT LOADING, 12-BIT DAC, PQFP64 |
| 封裝： | ROHS COMPLIANT, MS-026BCD, LQFP-64 |
| 文件頁數： | 74/88頁 |
| 文件大?。?/td> | 1066K |
| 代理商： | ADV7341BSTZ |
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ADV7340/ADV7341
APPENDIX 3—SD CLOSED CAPTIONING
Subaddress 0
x
91 to Subaddress 0
x
94
The ADV7340/ADV7341 support closed captioning conforming
to the standard television synchronizing waveform for color
transmission. Closed captioning is transmitted during the
blanked active line time of Line 21 of the odd fields and
Line 284 of the even fields.
Closed captioning consists of a 7-cycle sinusoidal burst that is
frequency- and phase-locked to the caption data. After the clock
run-in signal, the blanking level is held for two data bits and is
followed by the Logic 1 start bit. Sixteen bits of data follow the
start bit. These consist of two 8-bit bytes, seven data bits, and one
odd parity bit. The data for these bytes is stored in the SD closed
captioning registers (Subaddress 0x93 to Subaddress 0x94).
The ADV7340/ADV7341 also support the extended closed
captioning operation, which is active during even fields and
encoded on Scan Line 284. The data for this operation is stored
in the SD closed captioning registers (Subaddress 0x91 to
Subaddress 0x92).
Rev. 0 | Page 74 of 88
The ADV7340/ADV7341 automatically generate all clock run-
in signals and timing that support closed captioning on Line 21
and Line 284. All pixels inputs are ignored on Line 21 and Line
284 if closed captioning is enabled.
The FCC Code of Federal Regulations (CFR) 47 Section 15.119
and EIA-608 describe the closed captioning information for
Line 21 and Line 284.
The ADV7340/ADV7341 use a single buffering method. This
means that the closed captioning buffer is only 1-byte deep.
Therefore, there is no frame delay in outputting the closed
captioning data, unlike other 2-byte deep buffering systems.
The data must be loaded one line before it is output on Line 21
and Line 284. A typical implementation of this method is to use
VSYNC to interrupt a microprocessor, which in turn loads the
new data (2 bytes) in every field. If no new data is required for
transmission, 0s must be inserted in both data registers; this is
called nulling. It is also important to load control codes, all of
which are double bytes, on Line 21. Otherwise, a TV does not
recognize them. If there is a message such as “Hello World”
that has an odd number of characters, it is important to add a
blank character at the end to make sure that the end-of-caption,
2-byte control code lands in the same field.
D0 TO D6
D0 TO D6
10.5 ± 0.25μs
12.91μs
7 CYCLES OF
0.5035MHz
CLOCK RUN-IN
REFERENCE COLOR BURST
(9 CYCLES)
FREQUENCY = F
= 3.579545MHz
AMPLITUDE = 40 IRE
10.003μs
50 IRE
40 IRE
27.382μs
33.764μs
BYTE 1
BYTE 0
TWO 7-BIT + PARITY
ASCII CHARACTERS
(DATA)
S
T
A
R
T
P
A
R
I
T
Y
P
A
R
I
T
Y
0
Figure 99. SD Closed Captioning Waveform, NTSC
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| ADV7342 | Multiformat Video Encoder Six, 11-Bit, 297 MHz DACs |
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相關代理商/技術參數 |
參數描述 |
|---|---|
| ADV7341EBZ | 制造商:AD 制造商全稱:Analog Devices 功能描述:Multiformat Video Encoder, Six 12-Bit Noise Shaped Video㈢ DACS |
| ADV7342 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Multiformat Video Encoder Six, 11-Bit, 297 MHz DACs |
| ADV7342BSTZ | 制造商:AD 制造商全稱:Analog Devices 功能描述:Multiformat Video Encoder Six, 11-Bit, 297 MHz DACs |
| ADV7343 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Multiformat Video Encoder Six, 11-Bit, 297 MHz DACs |
| ADV7343BSTZ | 功能描述:IC ENCODER VIDEO W/DAC 64-LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編碼器，解碼器，轉換器 系列:- 產品變化通告:Development Systems Discontinuation 26/Apr/2011 標準包裝:1 系列:- 類型:編碼器 應用:DVB-S.2 系統 電壓 - 電源，模擬:- 電壓 - 電源，數字:- 安裝類型:- 封裝/外殼:模塊 供應商設備封裝:模塊 包裝:散裝 其它名稱:Q4645799 |
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