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參數資料
| 型號： | AN10E40 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Field Programmable Analog Array |
| 中文描述： | 現場可編程模擬陣列 |
| 文件頁數： | 22/36頁 |
| 文件大小： | 293K |
| 代理商： | AN10E40 |
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18
Pin Out Description
The signal naming convention holds that active low signals are named with a “b” suffix.
Pin
1
Pin name
Type
Description
ARRAYCLKOUT
Digital Output
Programming allows one of the 4 internal clocks
to be presented here.
Configuration mode control pin
0 = Micro Peripheral Interface Mode (Micro)
1 = Boot From Serial ROM (BFR)
Configuration mode control pin
0 = Use Internal Clock (CFG_CLK is an output,
running at 1/8 internal ring oscillator frequency.)
1 = Use External Clock (CFG_CLK is the clock
input to the configuration logic.)
Configuration logic clock
Direction controlled by MODE[2]
SPROM Configuration clock output
1/2 frequency of CFG_CLK.
Data pins used for loading configuration data
and checking status. DATA[0] is used for serial
BFR mode, and the entire byte width is used in
Micro mode.
2
MODE[1]
Digital Input
3
MODE[2]
Digital Input
4
CFG_CLK
Digital I/O
5
DCLK
Digital Output
6
7
8
9
10
11
12
13
14
15
16
17
18
19
DATA[0]
DATA[1]
DATA[2]
DATA[3]
DATA[4]
DATA[5]
DATA[6]
DATA[7]
F[1] (ERRb, RDb)
F[2] (MEMCEb, WRb)
F[0] (BFRb, CSb)
F[3] (PWRUP, RS)
F[4] (END, BUSY)
OPAMP_DISABLE
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
O.D. Out, Digital In
Digital Out, Digital In
Digital Input
Digital Input
Digital Output
Digital Input
Configuration Function pins
(BFR mode function, Micro mode function)
F[1] is an Open Drain output. In multi-FPAA
systems, all the ERRb lines can be tied together
to provide a single error indicator.
Op-Amp disable input (normally tied to Vss, not
usually utilized in systems)
Takes precedence over BFR’s PWRUP input
and Micro’s Function Register Bit Position 4
(Analog Enable)
0 = Analog circuitry enabled
1 = Analog circuitry disabled
Chip RESET
Falling edge detected to start Reset
Unbuffered Analog input
Buffered Analog input
Buffered Analog output
Uncommitted op-amp output
Uncommitted op-amp input
Buffered op-amp output
Buffered Analog input
Unbuffered Analog input
Analog VDD, 5 Volts
Analog VSS, 0 Volts
Substrate VSS, 0 Volts
Unbuffered Analog input
Buffered Analog input
Buffered analog output
Buffered op-amp output
20
RESETb
Digital Input
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
IOLDX
IOLDY
IOLDZ
IOLDZ2
IOLDY2
IOLCZ
IOLCY
IOLCX
AVDD
AVSS
SVSS
IOLBX
IOLBY
IOLBZ
IOLAZ
Analog Input
Analog Input
Analog Output
Analog Output
Analog Input
Analog Output
Analog Input
Analog Input
Power Supply
Power Supply
Power Supply
Analog Input
Analog Input
Analog Output
Analog Output
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