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參數資料
| 型號： | AN10E40 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Field Programmable Analog Array |
| 中文描述： | 現場可編程模擬陣列 |
| 文件頁數： | 9/36頁 |
| 文件大小： | 293K |
| 代理商： | AN10E40 |
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AN10E40 Data Manual
5
specified to be 1 MHz. You are free to drive CLOCK into the array at up to 20 MHz, then program and use
CLOCK[3:0] individually as your circuits might require.
The AN10E40 is designed such that all IPmodules along an analog signal path should use the same clock. While it
is possible to mix clocks along a signal path, it should not be done without full understanding of sampled data
systems, the effects of oversampling, undersampling and aliasing and careful consideration of possible unintended
consequences. The edges of divided clocks are synchronized only with the master clock edges, and therefor the
phase relationship of divided clocks is not guaranteed. For this reason, users are cautioned not to utilize two equal
frequency divided clocks with the exception of clocks that have a divisor of one are therefor equal to the master
clock.
Please note, the performance estimates for a placed IPmodule are based upon the known clock assignment and
divider ratios at the time of IPmodule placement. Any change in the top level chip clock settings may of course
affect your circuit behavior.
This section described the CLOCK input pin, not to be confused with the configuration clock pin CFG_CLK,
discussed below in the section Configuration Clock.
Voltage Reference
The AN10E40 provides a convenient programmable on-chip voltage reference. When your circuit requires a
comparator function against a known value, this voltage reference is easily programmed and enabled.
The value programmed into the Voltage Reference is always specified relative to signal ground. On the AN10E40,
signal ground is at VMR (see Voltage Mid-Rail Generator below).
Voltage Mid-Rail Generator
All analog signals within the array are referenced to Voltage Mid-Rail (VMR), typically 2.5 V with respect to AVSS.
The VMR signal is generated on chip, filtered with an external capacitor then routed back into the array for use by
the CABs.
Figure 4. Filtering OpAmpVMR
The RC network provides a simple but effective low pass filter for the on-chip OpAmpVMR signal. It is not
recommended that OpAmpVMR be loaded externally with anything other than a low leakage current 100 nF
capacitor.
VMR is provided as a convenience outlet for the VMR signal. The system is designed only to drive the RC filter
network. If your system requires use of VMR, it is recommended that you first buffer it with a high impedance
amplifier. Conversely, should your system design establish a requirement for generating signal ground (VMR)
The recommended connections are:
10 nF between CEXT and a quiet ground node
VMR unloaded
100 nF between OPAMPVMR and a quiet ground node
100nF
Bandgap
Reference
Generator
VMR
OpAmpVMR
Cext
10nF
To CABs
50
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