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參數(shù)資料
| 型號： | ATT3020-50J84I |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | FPGA |
| 英文描述： | Field-Programmable Gate Arrays |
| 中文描述： | 現(xiàn)場可編程門陣列 |
| 文件頁數(shù)： | 22/80頁 |
| 文件大小： | 528K |
| 代理商： | ATT3020-50J84I |
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Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
22
Lucent Technologies Inc.
Configuration Modes
Master Mode
In master mode, the FPGA automatically loads configu-
ration data from an external memory device. There are
three master modes which use the internal timing
source to supply the configuration clock (CCLK) to time
the incoming data. Serial master mode uses serial con-
figuration data supplied to data-in (DIN) from a syn-
chronous serial source such as the serial configuration
PROM shown in Figure 21. Parallel master low and
master high modes automatically use parallel data sup-
plied to the D[7:0] pins in response to the 16-bit
address generated by the FPGA. Figure 22 shows an
example of the parallel master mode connections
required. The FPGA HEX starting address is 0000 and
increments for master low mode, and it is FFFF and
decrements for master high mode. These two modes
provide address compatibility with microprocessors
which begin execution from opposite ends of memory.
For master high or low, data bytes are read in parallel
by each read clock (
RCLK
) and internally serialized by
the configuration clock. As each data byte is read, the
least significant bit of the next byte, D0, becomes the
next bit in the internal serial configuration word. One
master mode FPGA can be used to interface the
configuration program-store, and pass additional
concatenated configuration data to additional FPGAs in
a serial daisy-chain fashion. CCLK is provided for the
slaved devices, and their serialized data is supplied
from DOUT to DIN, DOUT to DIN, etc.
Note: The serial configuration PROM supports automatic loading of configuration programs up to 36/64/128 Kbits. Multiple devices can be
cascaded to support additional FPGAs. An early DONE inhibits the data output one CCLK cycle before the FPGA I/O becomes active.
Figure 21. Master Serial Mode
5-3112(C)
DURING CONFIGURATION
THE 5 k
M2 PULL-DOWN
RESISTOR OVERCOMES THE
INTERNAL PULL-UP,
BUT IT ALLOWS M2 TO
BE USER I/O.
M0
M1
PWRDWN
+5 V
DOUT
M2
HDC
LDC
OTHER
I/O PINS
ATT3000
SERIES
FPGA
GENERAL-
PURPOSE
USER I/O
PINS
*
*
RESET
SYSTEM RESET
D/P
INIT
CCLK
DIN
CE
OE/RESET
CLK
DATA
ATT1700A
CEO
(HIGH RESETS THE ADDRESS POINTER)
CASCADED
ATT1700A
MEMORY
OPTIONAL
IDENTICAL SLAVE
FPGAs CONFIGURED
THE SAME
CE
OE/RESET
CLK
DATA
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