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參數(shù)資料
| 型號： | ATT3020-50J84I |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | FPGA |
| 英文描述： | Field-Programmable Gate Arrays |
| 中文描述： | 現(xiàn)場可編程門陣列 |
| 文件頁數(shù)： | 26/80頁 |
| 文件大小： | 528K |
| 代理商： | ATT3020-50J84I |
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Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
26
Lucent Technologies Inc.
Configuration Modes
(continued)
Daisy Chain
The
ORCA
Foundry for ATT3000 Development System
is used to create a composite configuration bit stream
for selected FPGAs including a preamble, a length
count for the total bit stream, multiple concatenated
data programs, a postamble, plus an additional fill bit
per device in the serial chain. After loading and passing
on the preamble and length count to a possible daisy
chain, a lead device will load its configuration data
frames while providing a high DOUT to possible down-
stream devices as shown in Figure 25. Loading contin-
ues while the lead device has received its configuration
program and the current length count has not reached
the full value. Additional data is passed through the
lead device and appears on the data out (DOUT) pin in
serial form. The lead device also generates the CCLK
to synchronize the serial output data and data in of
downstream FPGAs. Data is read in on DIN of slave
devices by the positive edge of CCLK and shifted out
the DOUT on the negative edge of CCLK. A parallel
master mode device uses its internal timing generator
to produce an internal CCLK of eight times its EPROM
address rate, while a peripheral mode device produces
a burst of eight CCLKs for each chip select and write-
strobe cycle. The internal timing generator continues to
operate for general timing and synchronization of
inputs in all modes.
Figure 25. Master Mode with Daisy-Chained Slave Mode Devices
5-3116(F)
M0 M1PWRDWN
FPGA
MASTER
+5 V
HDC
LDC
OTHER
I/O PINS
RCLK
GENERAL-
PURPOSE
USER I/O
PINS
5 k
M2
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
8
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
EPROM
OE
CE
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D/P
+5 V
RESET
REPROGRAM
SYSTEM
RESET
OPEN COLLECTOR
M0 M1PWRDWN
+5 V
5 k
HDC
LDC
OTHER
I/O PINS
GENERAL-
PURPOSE
USER I/O
M2
INIT
DIN
CCLK
D/P
RESET
DOUT
M0 M1PWRDWN
+5 V
5 k
HDC
LDC
OTHER
I/O PINS
GENERAL-
PURPOSE
USER I/O
M2
DIN
CCLK
D/P
RESET
DOUT
FPGA
SLAVE #1
FPGA
SLAVE #n
5 k
EACH
+5 V
INIT
CCLK
DOUT
A15
A14
A13
A12
A11
INIT
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|---|---|
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