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參數資料
| 型號： | ATT3020-50J84I |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | FPGA |
| 英文描述： | Field-Programmable Gate Arrays |
| 中文描述： | 現場可編程門陣列 |
| 文件頁數： | 30/80頁 |
| 文件大?。?/td> | 528K |
| 代理商： | ATT3020-50J84I |
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Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
30
Lucent Technologies Inc.
Performance
(continued)
Logic Block Performance
Logic block performance is expressed as the propaga-
tion time from the interconnect point at the input of the
combinatorial logic to the output of the block in the
interconnect area. Combinatorial performance is inde-
pendent of the specific logic function because of the
table look-up based implementation. Timing is different
when the combinatorial logic is used in conjunction with
the storage element. For the combinatorial logic func-
tion driving the data input of the storage element, the
critical timing is data setup relative to the clock edge
provided to the flip-flop element. The delay from the
clock source to the output of the logic block is critical in
the timing of signals produced by storage elements.
Loading of a logic block output is limited only by the
resulting propagation delay of the larger interconnect
network. Speed performance of the logic block is a
function of supply voltage and temperature (see
Figures 28 and 29).
Interconnect Performance
Interconnect performance depends on the routing
resource used to implement the signal path. As dis-
cussed earlier, direct interconnect from block to block
provides a fast path for a signal. The single metal
segment used for long lines exhibits low resistance
from end to end, but relatively high capacitance.
Signals driven through a programmable switch will
have the additional impedance of the switch added to
their normal drive impedance.
General-purpose interconnect performance depends
on the number of switches and segments used, the
presence of the bidirectional repowering buffers, and
the overall loading on the signal path at all points along
the path. In calculating the worst-case timing for a
general interconnect path, the timing calculator portion
of the
ORCA
Foundry
Development System accounts
for all of these elements.
As an approximation, interconnect timing is propor-
tional to the summation of totals of local metal seg-
ments beyond each programmable switch. In effect, the
time is a sum of R-C time each approximated by an R
times the total C it drives. The R of the switch and the C
of the interconnect are functions of the particular
device performance grade.
For a string of three local interconnects, the approxi-
mate time at the first segment after the first switch
resistance would be three units—an additional two
units after the next switch plus an additional unit after
the last switch in the chain. The interconnect R-C chain
terminates at each repowering buffer. The capacitance
of the actual block inputs is not significant; the capaci-
tance is in the interconnect metal and switches.
Figure 30 illustrates this.
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