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參數資料
| 型號： | ATT3042-70H68I |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | FPGA |
| 英文描述： | Field-Programmable Gate Arrays |
| 中文描述： | 現場可編程門陣列 |
| 文件頁數： | 34/80頁 |
| 文件大?。?/td> | 528K |
| 代理商： | ATT3042-70H68I |
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Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
34
Lucent Technologies Inc.
Pin Information
Table 4. Permanently Dedicated Pins
Symbol
Name/Description
V
CC
Two to eight (depending on package type) connections to the nominal +5 V supply voltage. All
must be connected.
GND
Two to eight (depending on package type) connections to ground. All must be connected.
PWRDWN
A low on this CMOS compatible input stops all internal activity to minimize V
CC
power, and puts
all output buffers in a high-impedance state; configuration is retained. When the
PWRDWN
pin
returns high, the device returns to operation with the same sequence of buffer enable and
DONE/
PROG
as at the completion of configuration. All internal storage elements are reset. If
not used,
PWRDWN
must be tied to V
CC
.
RESET
This is an active-low input which has three functions:
I
Prior to the start of configuration, a low input will delay the start of the configuration process.
An internal circuit senses the application of power and begins a minimal time-out cycle. When
the time-out and
RESET
are complete, the levels of the M lines are sampled and configuration
begins.
I
If
RESET
is asserted during a configuration, the FPGA is reinitialized and will restart the con-
figuration at the termination of
RESET
.
I
If
RESET
is asserted after configuration is complete, it will provide an asynchronous reset of all
IOB and CLB storage elements of the FPGA.
CCLK
Configuration Clock
. During configuration, this is an output of an FPGA in master mode or
peripheral mode. FPGAs in slave mode use it as a clock input. During a readback operation, it is
a clock input for the configuration data being filtered out.
DONE/
PROG
DONE Output
. Configurable as open drain with or without an internal pull-up resistor. At the
completion of configuration, the circuitry of the FPGA becomes active in a synchronous order,
and DONE may be programmed to occur one cycle before or after that occurs. Once configura-
tion is done, a high-to-low transition of this pin will cause an initialization of the FPGA and start a
reconfiguration.
M0/RTRIG
Mode 0
. This input, M1, and M2 are sampled before the start of configuration to establish the
configuration mode to be used. After configuration is complete, a low-to-high transition acts as a
read trigger to initiate a readback of configuration and storage-element data clocked by CCLK.
M1/
RDATA
Mode 1
. This input, M0, and M2 are sampled before the start of configuration to establish the
configuration mode to be used. After configuration is complete, this pin is the active-low output of
the readback data.
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