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參數資料
型號: CAT6095VP2-GT4
廠商: ON Semiconductor
文件頁數: 3/15頁
文件大小: 151K
描述: IC TEMP SENSOR STAND ALONE 8TDFN
標準包裝: 1
功能: 溫度監控系統(傳感器)
傳感器類型: 內部
感應溫度: -40°C ~ 125°C
精確度: ±3°C(最小值)
拓撲: ADC(三角積分型),比較器,寄存器庫
輸出類型: I²C?/SMBus?
輸出警報:
輸出風扇:
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 8-WFDFN 裸露焊盤
供應商設備封裝: 8-TDFN(2x3)
包裝: 標準包裝
其它名稱: CAT6095VP2-GT4OSDKR
CAT6095
http://onsemi.com
3
Table 4. A.C. CHARACTERISTICS (V
CC
 = 3.3 V ?10%, T
A
 = 40癈 to +125癈) (Note 3)
Symbol
Parameter
Min
Max
Units
F
SCL
 (Note 4)
Clock Frequency
10
400
kHz
t
HIGH
High Period of SCL Clock
600
ns
t
LOW
Low Period of SCL Clock
1300
ns
t
TIMEOUT
 (Note 4)
SMBus SCL Clock Low Timeout
25
35
ms
t
R
 (Note 5)
SDA and SCL Rise Time
300
ns
t
F
 (Note 5)
SDA and SCL Fall Time
300
ns
t
SU:DAT
 (Note 6)
Data Setup Time
100
ns
t
HD:DAT
 (Note 5)
Data Hold Time (for Input Data)
0
ns
Data Hold Time (for Output Data)
300
900
ns
t
SU:STA
START Condition Setup Time
600
ns
t
HD:STA
START Condition Hold Time
600
ns
t
SU:STO
STOP Condition Setup Time
600
ns
t
BUF
Bus Free Time Between STOP and START
1300
ns
T
i
Noise Pulse Filtered at SCL and SDA Inputs
100
ns
t
PU
 (Note 7)
Powerup Delay to Valid Temperature Recording
100
ms
3.  Timing reference points are set at 30%, respectively 70% of V
CC
, as illustrated in Figure 11. Bus loading must be such as to allow meeting
the V
IL
, V
OL
 as well as the various timing limits.
4.  The TS interface will reset itself and will release the SDA line if the SCL line stays low beyond the t
TIMEOUT
 limit. The timeout count is started
(and then restarted) on every negative transition of SCL in the time interval between START and STOP.
5.  In a WiredOR system (such as I
2
C or SMBus), SDA rise time is determined by bus loading. Since each bus pulldown device must be
able to sink the (external) bus pullup current (in order to meet the V
IL
 and/or V
OL
 limits), it follows that SDA fall time is inherently faster than
SDA rise time. SDA rise time can exceed the standard recommended t
R
 limit, as long as it does not exceed t
LOW
  t
HD:DAT
  t
SU:DAT
, where
t
LOW
 and t
HD:DAT
 are actual values (rather than spec limits). A shorter t
HD:DAT
 leaves more room for a longer SDA t
R
, allowing for a more
capacitive bus or a larger bus pullup resistor. At the minimum t
LOW
 spec limit of 1300 ns, the maximum t
HD:DAT
 of 900 ns demands a
maximum SDA t
R
 of 300 ns. The CAT6095s maximum t
HD:DAT
 is <700 ns, thus allowing for an SDA t
R
 of up to 500 ns at minimum t
LOW
.
6.  The minimum t
SU:DAT
 of 100 ns is a limit recommended by standards. The TS will accept a t
SU:DAT
 of 0 ns.
7.  The first valid temperature recording can be expected after t
PU
 at nominal supply voltage.
Table 5. PIN CAPACITANCE (T
A
 = 25癈, V
CC
 = 3.3 V, f = 1 MHz)
Symbol
Parameter
Test Conditions/Comments
Min
Max
Unit
C
IN
SDA, EVENT
 Pin Capacitance
V
IN
 = 0
8
pF
Input Capacitance (other pins)
V
IN
 = 0
6
pF
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