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參數資料
型號: CAT6095VP2-GT4
廠商: ON Semiconductor
文件頁數: 9/15頁
文件大?。?/td> 151K
描述: IC TEMP SENSOR STAND ALONE 8TDFN
標準包裝: 1
功能: 溫度監控系統(傳感器)
傳感器類型: 內部
感應溫度: -40°C ~ 125°C
精確度: ±3°C(最小值)
拓撲: ADC(三角積分型),比較器,寄存器庫
輸出類型: I²C?/SMBus?
輸出警報:
輸出風扇:
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 8-WFDFN 裸露焊盤
供應商設備封裝: 8-TDFN(2x3)
包裝: 標準包裝
其它名稱: CAT6095VP2-GT4OSDKR
CAT6095
http://onsemi.com
9
Table 6. TEMPERATURE SENSOR REGISTERS
Register Address
Register Name
PowerOn Default
Read/Write
0x00
Capability Register
0x007F
Read
0x01
Configuration Register
0x0000
Read/Write
0x02
High Limit Register
0x0000
Read/Write
0x03
Low Limit Register
0x0000
Read/Write
0x04
Critical Limit Register
0x0000
Read/Write
0x05
Temperature Data Register
Undefined
Read
0x06
Manufacturer ID Register
0x1B09
Read
0x07
Device ID/Revision Register
0x0813
Read
0x08 
Reserved


Table 7. CAPABILITY REGISTER
B15
B14
B13
B12
B11
B10
B9
B8
RFU
RFU
RFU
RFU
RFU
RFU
RFU
RFU
B7
B6
B5
B4
B3
B2
B1
B0
EVSD
TMOUT
RFU
TRES [1:0]
RANGE
ACC
EVENT
Bit
Description
B15:B8
Reserved for future use; can not be written; should be ignored; will typically read as 0
B7 (Note 8)
0:
Configuration register bit 4 is frozen upon setting Configuration register bit 8
(i.e. a TS shutdown freezes the EVENT
 output)
1:
Configuration register bit 4 is cleared upon setting Configuration register bit 8
(i.e. a TS shutdown deasserts the EVENT
 output)
B6
0:
The TS implements SMBus timeout within the range 10 to 60 ms
1:
The TS implements SMBus timeout within the range 25 to 35 ms
B5
0:
Pin A
0
 V
HV
 compliance required for RSWP/SPD compatibility not explicitly stated
1:
Pin A
0
 V
HV
 compliance required for RSWP/SPD compatibility explicitly stated
B4:B3
00:
LSB = 0.50癈 (9 bit resolution)
01:
LSB = 0.25癈 (10 bit)
10:
LSB = 0.125癈 (11 bit)
11:
LSB = 0.0625癈 (12 bit)
B2
0:
Positive Temperature Only
1:
Positive and Negative Temperature
B1
0:
?癈 over the active range and ?癈 over the operating range (Class C)
1:
?癈 over the active range and ?癈 over the monitor range (Class B)
B0
0:
Critical Temperature only
1:
Alarm and Critical Temperature
8.  Configuration Register bit 4 can be cleared (but not set) after Configuration Register bit 8 is set, by writing a 1 to Configuration Register
bit 5 (i.e. the EVENT
 output can be de-asserted during TS shut-down periods)
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