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參數(shù)資料
| 型號(hào)： | CDC9843DWR |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | PC MOTHERBOARD CLOCK SYNTHESIZER/DRIVER WITH 3-STATE OUTPUTS |
| 中文描述： | PC主板時(shí)鐘合成器/ 3驅(qū)動(dòng)態(tài)輸出 |
| 文件頁數(shù)： | 1/8頁 |
| 文件大小： | 124K |
| 代理商： | CDC9843DWR |
CDC9843
PC MOTHERBOARD CLOCK SYNTHESIZER/DRIVER
WITH 3-STATE OUTPUTS
SCAS559C – DECEMBER 1995 – REVISED OCTOBER 1996
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Provides System Clock Solution for
Pentium
/82430HX/82430VX and
PentiumPro 82440FX Chipsets
Four Host-Clock Outputs With
Programmable Frequency
(50 MHz, 60 MHz, and 66 MHz)
Six PCI Clock Outputs at Half-CPU
Frequency
One 48-MHz Universal Serial Bus (USB)
Clock Output
One 24-MHz Floppy Controller Output
Two 14.318-MHz Reference Clock Outputs
All Output Clock Frequencies Derived From
Single 14.31818-MHz Crystal Input
LVTTL-Compatible Inputs and Outputs
Internal Loop Filters for Phase-Lock Loops
Eliminate the Need for External
Components
Operates at 3.3-V V
CC
Packaged in Plastic Small-Outline Package
description
The CDC9843 is a high-performance clock synthesizer/driver that generates the system clocks necessary to
support Pentium
/82430HX/82430VX and PentiumPro 82440FX chipsets. Four host-clock outputs (HCLKn)
are programmable to one of three frequencies (50 MHz, 60 MHz, or 66 MHz) via the SEL0 and SEL1 control
inputs. Six PCI-clock outputs (PCLKn) are half the frequency of CPU clock outputs and are delayed 1 ns to
4 ns from the rising edge of the CPU clock. In addition, a universal serial bus (USB) clock output at 48 MHz
(SBCLK), a floppy controller clock at 24 MHz (FCCLK), and two 14.318-MHz reference clock outputs (REF0,
REF1) are provided.
All output frequencies are generated from a 14.318-MHZ crystal input. A reference clock input can be provided
at the X1 input instead of a crystal input.
Two phase-locked loops (PLLs) are used to generate the host clock frequency and the 48-MHz clock frequency.
On-chip loop filters and internal feedback eliminate the need for external components. The PCI-clock frequency
and floppy controller frequency are derived directly from the host-clock frequency and USB frequency,
respectively. The PLL circuit can be bypassed in the test mode (i.e., SEL0 = SEL1 = H) to distribute a test clock
provided at the X1 input.
The host- and PCI-clock outputs provide low-skew/low-jitter clock signals for reliable clock operation. All outputs
are 3 state and are enabled via OE.
Because the CDC9843 is based on PLL circuitry, it requires a stabilization time to achieve phase-lock of the PLL.
This stabilization time is required following power up and application of a fixed-frequency, fixed-phase signal
at the X1, as well as following any changes to the OE or SELn inputs.
Copyright
1996, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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V
CC
X1
X2
GND
OE
HCLK0
HCLK1
V
CC
HCLK2
HCLK3
GND
SEL1
SEL0
V
CC
REF0
REF1
V
CC
SBCLK
FCCLK
GND
PCLK0
PCLK1
V
CC
PCLK2
PCLK3
GND
PCLK4
PCLK5
DW PACKAGE
(TOP VIEW)
Pentium is a trademark of Intel Corporation.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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