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參數(shù)資料
| 型號(hào)： | CGS700TV |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Commercial Low Skew PLL 1 to 9 CMOS Clock Driver |
| 中文描述： | 商業(yè)低偏移鎖相環(huán)1至9的CMOS時(shí)鐘驅(qū)動(dòng)器 |
| 文件頁(yè)數(shù)： | 1/6頁(yè) |
| 文件大小： | 126K |
| 代理商： | CGS700TV |
TL/F/11955
C
September 1995
CGS700V
Commercial Low Skew PLL 1 to 9 CMOS Clock Driver
General Description
CGS700 is an off the shelf clock driver specifically designed
for today’s high speed processors. It provides low skew out-
puts which are produced at different frequencies from three
fixed input references. The XTALIN input pin is designed to
be driven from three distinct crystal oscillators running at
25 MHz, 33 MHz or 40 MHz.
The PLL, using a charge pump and an internal loop filter,
multiplies this input frequency to create a maximum output
frequency of four times the input.
The device includes a TRI-STATE
é
control pin to disable
the outputs while the PLL is still in lock. This function allows
for testing the board without having to wait to acquire the
lock once the testing is complete.
(continued)
Features
Y
Guaranteed and tested:
D 500 ps pin-to-pin skew (t
OSHL
and t
OSLH
) on 1X
outputs
Y
Guaranteed:
D 400 ps pin-to-pin skew (t
OSHL
and t
OSLH
) on
1Xoutputs
Y
Pentium
TM
and PowerPC
TM
compatible
Y
Output buffer of nine drivers for large fanout
Y
25 MHz–160 MHz output frequency range
Y
Outputs operating at 4X, 2X, 1X of the reference
frequency for multi-frequency bus applications
Y
Selectable output frequency
Y
TRI-STATE output control with the PLL is in the lock
state
Y
Internal loop filter to reduce noise and jitter
Y
Separate analog and digital V
CC
and Ground pins
Y
Low frequency test mode by disabling the PLL
Y
Implemented on National’s Core CMOS process
Y
Symmetric output current drive:
a
30 mA/
b
30 mA I
OL
/I
OH
Y
28-pin PCC for optimum skew performance
Y
Guaranteed 2k ESD protection
Connection Diagram
Pin Assignment for PLCC
TL/F/11955–1
See NS Package Number V28A
TRI-STATE
é
is a registered trademark of National Semiconductor Corporation.
PowerPC
TM
is a trademark of IBM.
Pentium
TM
is a trademark of Intel Corporation.
Pin Description
PLCC Package
Pin
Name
Description
1
V
CC
Digital V
CC
2
SKWSEL
Skew Test Selector Pin
3
CLK4
4X Clock Output
4
V
CC
Digital V
CC
5
XTALIN
Crystal Oscillator Input
6
GND
Digital Ground
7
CLK1D0
V
CC
1X Clock Output
8
Digital V
CC
9
CLK1D1
GND
1X Clock Output
10
Digital Ground
11
CLK1D2
TRI-STATE
1X Clock Output
12
Output TRI-STATE Control
13
SKWTST
Skew Testing Pin
14
CLK1D3
GND
1X Clock Output
15
Digital Ground
16
CLK1D4
V
CC
1X Clock Output
17
Digital V
CC
18
EXTCLK
External Test Clock
19
GNDA
Analog Ground
20
V
CCA
Analog V
CC
21
EXTSEL
External Clock Mux Selector
22
GND
Digital Ground
23
CLK1D5
V
CC
1X Clock Output
24
Digital V
CC
25
CLK1D6
CLK1SEL
1X Clock Output
26
CLK1 Multiplier Selector
27
GND
Digital Ground
28
CLK2
2X Clock Output
C
1996 National Semiconductor Corporation
RRD-B30M66/Printed in U. S. A.
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| CGS700V | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Commercial Low Skew PLL 1 to 9 CMOS Clock Driver |
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