
CHRONTEL
201-0000-027 Rev 2.2, 9/30/99 *Intel 810 and Intel 810E are Trademarks of Intel Corp
1
CH7008A
Digital PC to TV Encoder Features
Features
Support for low voltage interface to VGA controller
Universal digital interface accepts YCrCb (CCIR656)
or RGB (15, 16 or 24-bit multiplexed) video data in
both non-interlaced and interlaced formats
TrueScale
TM
rendering engine supports underscan
operations for various graphic resolutions
¥
Enhanced text sharpness and adaptive flicker removal
with up to 5-lines of filtering
Enhanced dot crawl control and area reduction
Fully programmable through I
2
C port
Supports NTSC, NTSC-EIA (Japan), and PAL (B, D,
G, H, I, M and N) TV formats
Provides Composite, S-Video and SCART outputs
Auto-detection of TV presence
Programmable power management
9-bit video DAC outputs
Complete Windows and DOS driver software
Offered in 44-pin PLCC, 44-pin TQFP
General Description
Chrontel’s CH7008 digital PC to TV encoder is a stand-
alone integrated circuit which provides a PC 99 compliant
solution for TV output on non-DVD enabled systems.
Suggested application use with the Intel 810 chipset &
Intel 810E chipset.* It provides a universal digital input
port to accept a pixel data stream from a compatible VGA
controller (or equivalent) and converts this directly into
NTSC or PAL TV format.
This circuit integrates a digital NTSC/PAL encoder with
9-bit DAC interface, and new adaptive flicker filter, and
high accuracy low-jitter phase locked loop to create
outstanding quality video. Through its TrueScale
TM
scaling and deflickering engine, the CH7008 supports full
vertical and horizontal underscan capability and operates
in 5 different resolutions including 640x480 and 800x600.
A new universal digital interface along with full
programmability make the CH7008 ideal for system-level
PC solutions. All features are software programmable
through a standard I
2
C port, to enable a complete PC
solution using a TV as the primary display.
Patent number 5,781,241
¥
Patent number 5,914,753
Figure 1: Functional Block Diagram
TRIPLE
DAC
PLL
RGB-YUV
CONVERTER
SYSTEM CLOCK
Y/R
CVBS/B
C/G
YUV-RGB CONVERTER
DIGITAL
INPUT
INTERFACE
I
2
C REGISTER &
CONTROL BLOCK
LINE
MEMORY
TRUE SCALE
SCALING &
DEFLICKERING
ENGINE
TIMING & SYNC
GENERATOR
NTSC/PAL
ENCODER
& FILTERS
D[11:0]
PIXEL DATA
XCLK*
H
V
XI/FIN
XO
P-OUT
SC
SD
RESET*
DS/BCO
ISET
CSYNC
GPIO[1:0]